Searched refs:OS_REG_READ (Results 1 - 25 of 103) sorted by relevance

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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/contrib/ath_hal/ar9300/
H A Dar9300_tx99_tgt.c150 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
157 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
164 OS_REG_WRITE(ah, AR_PHY_TST_DAC_CONST, OS_REG_READ(ah, AR_PHY_TST_DAC_CONST) | (0x7ff<<11) | 0x7ff);
165 OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, OS_REG_READ(ah, AR_PHY_TEST_CTL_STATUS) | (1<<7) | (1<<1));
166 OS_REG_WRITE(ah, AR_PHY_ADDAC_PARA_CTL, (OS_REG_READ(ah, AR_PHY_ADDAC_PARA_CTL) | (1<<31) | (1<<15)) & ~(1<<13));
171 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
174 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP)
176 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
180 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, OS_REG_READ(ah, AR_HORNET_CH0_TOP)
182 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, (OS_REG_READ(a
[all...]
H A Dar9300_recv.c34 return OS_REG_READ(ath, AR_HP_RXDP);
36 return OS_REG_READ(ath, AR_LP_RXDP);
91 __func__, OS_REG_READ(ah, AR_OBS_BUS_1));
122 org_value = OS_REG_READ(ah, AR_MACMISC);
134 OS_REG_READ(ah, AR_DMADBG_7));
142 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) {
153 OS_REG_READ(ah, AR_CR),
154 OS_REG_READ(ah, AR_DIAG_SW));
212 u_int32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
213 u_int32_t phybits = OS_REG_READ(a
[all...]
H A Dar9300_interrupts.c42 host_isr = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE));
47 host_isr = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE));
124 async_cause = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE));
131 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
134 isr = OS_REG_READ(ah, AR_ISR);
148 ah->ah_intrstate[0] = OS_REG_READ(ah, AR_ISR);
149 ah->ah_intrstate[1] = OS_REG_READ(ah, AR_ISR_S0);
150 ah->ah_intrstate[2] = OS_REG_READ(ah, AR_ISR_S1);
151 ah->ah_intrstate[3] = OS_REG_READ(ah, AR_ISR_S2);
152 ah->ah_intrstate[4] = OS_REG_READ(a
[all...]
H A Dar9300_gpio.c402 gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN));
463 reg_val = OS_REG_READ(ah, regs[i]);
477 reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL));
490 reg_val = OS_REG_READ(ah, regs[i]);
508 return OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL));
530 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR));
580 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT)));
583 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN)));
586 OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT)));
589 OS_REG_READ(a
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H A Dar9300_misc.c314 tsf = OS_REG_READ(ah, AR_TSF_U32);
315 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
332 return OS_REG_READ(ah, AR_TSF_L32);
338 return OS_REG_READ(ah, AR_TSF2_L32);
350 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
390 reg = OS_REG_READ(ah, AR_STA_ID1);
407 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
411 return (OS_REG_READ(ah, AR_TSF_U32) ^
412 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
429 v = OS_REG_READ(a
[all...]
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5416/
H A Dar5416_eeprom.c39 OS_REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
43 *data = MS(OS_REG_READ(ah, AR_EEPROM_STATUS_DATA),
H A Dar5416_interrupts.c47 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
51 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
88 isr = OS_REG_READ(ah, AR_ISR);
90 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
91 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
92 isr = OS_REG_READ(ah, AR_ISR);
98 o_sync_cause = sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
108 ah->ah_intrstate[1] = OS_REG_READ(ah, AR_ISR_S0);
109 ah->ah_intrstate[2] = OS_REG_READ(ah, AR_ISR_S1);
110 ah->ah_intrstate[3] = OS_REG_READ(a
[all...]
H A Dar5416_gpio.c74 tmp = OS_REG_READ(ah, addr);
126 reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
151 reg = OS_REG_READ(ah, AR_GPIO_OE_OUT);
171 reg = OS_REG_READ(ah, AR_GPIO_IN_OUT);
195 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9287_GPIO_IN_VAL);
197 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR9285_GPIO_IN_VAL);
199 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR928X_GPIO_IN_VAL);
201 bits = MS(OS_REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL);
219 val = MS(OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE),
224 mask = MS(OS_REG_READ(a
[all...]
H A Dar5416_spectral.c55 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
69 val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
72 val = OS_REG_READ(ah, AR_RX_FILTER);
92 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
157 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
168 val = OS_REG_READ(ah, AR_PHY_RADAR_1);
177 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
186 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
198 val = OS_REG_READ(ah, AR_PHY_SPECTRAL_SCAN);
202 val = OS_REG_READ(a
[all...]
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5212/
H A Dar5212_interrupts.c43 return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE);
62 isr = OS_REG_READ(ah, AR_ISR);
65 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
77 isr = OS_REG_READ(ah, AR_ISR_RAC);
91 isr0 = OS_REG_READ(ah, AR_ISR_S0_S);
94 isr1 = OS_REG_READ(ah, AR_ISR_S1_S);
116 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
117 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
118 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
119 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(a
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H A Dar5212_recv.c39 return OS_REG_READ(ath, AR_RXDP);
51 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
77 OS_REG_READ(ah, AR_CR),
78 OS_REG_READ(ah, AR_DIAG_SW));
96 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
110 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
136 val = OS_REG_READ(ah, AR_MCAST_FIL1);
139 val = OS_REG_READ(ah, AR_MCAST_FIL0);
156 val = OS_REG_READ(ah, AR_MCAST_FIL1);
159 val = OS_REG_READ(a
[all...]
H A Dar5212_gpio.c50 OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio));
64 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio))
80 reg = OS_REG_READ(ah, AR_GPIODO);
95 uint32_t val = OS_REG_READ(ah, AR_GPIODI);
112 val = OS_REG_READ(ah, AR_GPIOCR);
H A Dar5212_eeprom.c50 *data = OS_REG_READ(ah, AR_EEPROM_DATA) & 0xffff;
H A Dar5212_power.c59 scr = OS_REG_READ(ah, AR_SCR);
63 __func__, scr, OS_REG_READ(ah, AR_PCICFG));
71 val = OS_REG_READ(ah, AR_PCICFG);
168 return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);
179 return (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_SPWR_DN) != 0;
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5211/
H A Dar5211_recv.c39 return OS_REG_READ(ah, AR_RXDP);
51 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
75 , OS_REG_READ(ah, AR_CR)
76 , OS_REG_READ(ah, AR_DIAG_SW)
92 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
102 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
127 val = OS_REG_READ(ah, AR_MCAST_FIL1);
130 val = OS_REG_READ(ah, AR_MCAST_FIL0);
147 val = OS_REG_READ(ah, AR_MCAST_FIL1);
150 val = OS_REG_READ(a
[all...]
H A Dar5211_interrupts.c38 return OS_REG_READ(ah, AR_INTPEND) != 0;
55 isr = OS_REG_READ(ah, AR_ISR_RAC);
85 AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S);
86 AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S);
87 AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S);
88 AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S);
89 AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S);
126 (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */
H A Dar5211_beacon.c41 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
110 val = OS_REG_READ(ah, AR_STA_ID1);
135 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
148 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
164 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5312/
H A Dar5315_gpio.c47 (OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio))
64 (OS_REG_READ(ah, gpioOffset+AR5315_GPIODIR) &~ AR5315_GPIODIR_M(gpio))
81 reg = OS_REG_READ(ah, gpioOffset+AR5315_GPIODO);
98 uint32_t val = OS_REG_READ(ah, gpioOffset+AR5315_GPIODI);
116 val = OS_REG_READ(ah, gpioOffset+AR5315_GPIOINT);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar9002/
H A Dar9285_cal.c74 regList[i][1] = OS_REG_READ(ah, regList[i][0]);
76 regVal = OS_REG_READ(ah, 0x7834);
79 regVal = OS_REG_READ(ah, 0x9808);
95 ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
104 regVal = OS_REG_READ(ah, 0x7834);
108 regVal = OS_REG_READ(ah, 0x7834);
110 reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
117 reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
119 offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
120 offs_0 = MS(OS_REG_READ(a
[all...]
H A Dar9285.c48 nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
55 nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
H A Dar9287_cal.c60 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
H A Dar9287_olc.c72 rddata = OS_REG_READ(ah, AR_PHY_TX_PWRCTRL4);
142 tmpVal = OS_REG_READ(ah, 0xa270);
149 tmpVal = OS_REG_READ(ah, 0xb270);
157 tmpVal = OS_REG_READ(ah, 0xa398);
167 tmpVal = OS_REG_READ(ah, 0xb398);
/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/ath_hal/ar5210/
H A Dar5210_recv.c39 return OS_REG_READ(ah, AR_RXDP);
72 if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
78 ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
79 ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW));
91 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
101 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
126 val = OS_REG_READ(ah, AR_MCAST_FIL1);
129 val = OS_REG_READ(ah, AR_MCAST_FIL0);
146 val = OS_REG_READ(ah, AR_MCAST_FIL1);
149 val = OS_REG_READ(a
[all...]
H A Dar5210_misc.c72 (void) OS_REG_READ(ah, AR_EP_AIR(off)); /* activate read op */
79 *data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff;
168 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
183 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))
199 reg = OS_REG_READ(ah, AR_GPIODO);
214 uint32_t val = OS_REG_READ(ah, AR_GPIODI);
228 uint32_t val = OS_REG_READ(ah, AR_GPIOCR);
253 val = OS_REG_READ(ah, AR_PCICFG);
277 uint32_t val = OS_REG_READ(ah, AR_STA_ID1);
284 uint32_t val = OS_REG_READ(a
[all...]
H A Dar5210_beacon.c38 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
101 val = OS_REG_READ(ah, AR_STA_ID1);
129 (OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA)
143 OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
159 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))

Completed in 193 milliseconds

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