Searched refs:tiling_flags (Results 1 - 17 of 17) sorted by relevance

/freebsd-10.0-release/sys/dev/drm2/radeon/
H A Dradeon_object.c386 lobj->tiling_flags = bo->tiling_flags;
410 if (!bo->tiling_flags)
449 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
471 uint32_t tiling_flags, uint32_t pitch)
479 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
480 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
481 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
482 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
483 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIF
470 radeon_bo_set_tiling_flags(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch) argument
530 radeon_bo_get_tiling_flags(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch) argument
[all...]
H A Dradeon_fb.c112 u32 tiling_flags = 0; local
140 tiling_flags = RADEON_TILING_MACRO;
145 tiling_flags |= RADEON_TILING_SWAP_32BIT;
148 tiling_flags |= RADEON_TILING_SWAP_16BIT;
154 if (tiling_flags) {
156 tiling_flags | RADEON_TILING_SURFACE,
H A Dradeon_object.h147 u32 tiling_flags, u32 pitch);
149 u32 *tiling_flags, u32 *pitch);
H A Dr200.c222 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
224 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
294 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
296 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
H A Dr300.c690 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
692 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
694 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
759 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
761 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
763 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
844 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
846 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
848 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
H A Dradeon_legacy_crtc.c385 uint32_t tiling_flags; local
439 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
441 if (tiling_flags & RADEON_TILING_MICRO)
459 if (tiling_flags & RADEON_TILING_MACRO) {
475 if (tiling_flags & RADEON_TILING_MACRO) {
H A Devergreen_cs.c95 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) argument
97 if (tiling_flags & RADEON_TILING_MACRO)
99 else if (tiling_flags & RADEON_TILING_MICRO)
1391 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1392 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1393 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1396 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1576 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1577 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1594 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
[all...]
H A Datombios_crtc.c1077 uint32_t fb_format, fb_pitch_pixels, tiling_flags; local
1117 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1150 if (tiling_flags & RADEON_TILING_MACRO) {
1173 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1178 } else if (tiling_flags & RADEON_TILING_MICRO)
1280 uint32_t fb_format, fb_pitch_pixels, tiling_flags; local
1318 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1356 if (tiling_flags & RADEON_TILING_MACRO)
1358 else if (tiling_flags & RADEON_TILING_MICRO)
1361 if (tiling_flags
[all...]
H A Dr100.c1232 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1234 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1685 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1687 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1766 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1768 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
3158 uint32_t tiling_flags, uint32_t pitch,
3165 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3168 if (tiling_flags & RADEON_TILING_MACRO)
3171 if (tiling_flags
3157 r100_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size) argument
[all...]
H A Dr600_cs.c1173 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1272 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1275 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1603 u32 tiling_flags)
1625 if (tiling_flags & RADEON_TILING_MACRO)
1627 else if (tiling_flags & RADEON_TILING_MICRO)
2093 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2095 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2111 reloc->lobj.tiling_flags);
1598 r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, struct radeon_bo *texture, struct radeon_bo *mipmap, u64 base_offset, u64 mip_offset, u32 tiling_flags) argument
H A Dradeon_drm.h830 uint32_t tiling_flags; member in struct:drm_radeon_gem_set_tiling
836 uint32_t tiling_flags; member in struct:drm_radeon_gem_get_tiling
H A Dradeon_gem.c414 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
435 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
H A Dradeon.h213 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
342 u32 tiling_flags; member in struct:radeon_bo
364 u32 tiling_flags; member in struct:radeon_bo_list
1260 uint32_t tiling_flags, uint32_t pitch,
H A Dradeon_asic.h94 uint32_t tiling_flags, uint32_t pitch,
328 uint32_t tiling_flags, uint32_t pitch,
H A Dradeon_display.c362 u32 tiling_flags, pitch_pixels; local
420 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
428 if (tiling_flags & RADEON_TILING_MACRO) {
H A Devergreen.c54 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, argument
58 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
59 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
60 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
61 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
H A Dr600.c2764 uint32_t tiling_flags, uint32_t pitch,
2763 r600_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size) argument

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