/freebsd-10.0-release/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/ |
H A D | tst.signedkeyspos.d | 82 @i32["mouse", -2] = sum(-2); 83 @i32["bear", -2] = sum(-22); 84 @i32["cat", -2] = sum(-222); 85 @i32["mouse", -1] = sum(-1); 86 @i32["bear", -1] = sum(-11); 87 @i32["cat", -1] = sum(-111); 88 @i32["mouse", 0] = sum(0); 89 @i32["bear", 0] = sum(10); 90 @i32["cat", 0] = sum(100); 91 @i32["mous [all...] |
H A D | tst.signedkeys.d | 107 @i32[-2] = sum(-2); 108 @i32[-1] = sum(-1); 109 @i32[0] = sum(0); 110 @i32[1] = sum(1); 111 @i32[2] = sum(2);
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/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 53 /// i32. 55 return CurDAG->getTargetConstant(Imm, MVT::i32); 93 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 94 Offset = CurDAG->getTargetConstant(0, MVT::i32); 103 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 104 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); 122 MVT::i32, MskSize); 129 SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 143 return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, [all...] |
H A D | XCoreISelLowering.cpp | 72 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); 84 // Use i32 for setcc operations results (slt, sgt, ...). 89 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 91 setOperationAction(ISD::ADDC, MVT::i32, Expand); 92 setOperationAction(ISD::ADDE, MVT::i32, Expand); 93 setOperationAction(ISD::SUBC, MVT::i32, Expand); 94 setOperationAction(ISD::SUBE, MVT::i32, Expand); 102 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 103 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custo [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32; 67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 68 DAG.getConstant(SrcOff, MVT::i32)), 79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 80 DAG.getConstant(DstOff, MVT::i32)), 106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 107 DAG.getConstant(SrcOff, MVT::i32)), 129 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 130 DAG.getConstant(DstOff, MVT::i32)), 169 // Extend or truncate the argument to be an i32 valu [all...] |
H A D | ARMISelDAGToDAG.cpp | 84 /// getI32Imm - Return a target constant of type i32 with the specified 87 return CurDAG->getTargetConstant(Imm, MVT::i32); 292 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 405 Srl = CurDAG->getNode(ISD::SRL, Srl.getDebugLoc(), MVT::i32, 407 CurDAG->getConstant(Srl_imm+TZ, MVT::i32)); 408 N1 = CurDAG->getNode(ISD::AND, N1.getDebugLoc(), MVT::i32, 409 Srl, CurDAG->getConstant(And_imm, MVT::i32)); 410 N1 = CurDAG->getNode(ISD::SHL, N1.getDebugLoc(), MVT::i32, 411 N1, CurDAG->getConstant(TZ, MVT::i32)); 493 MVT::i32); [all...] |
/freebsd-10.0-release/sys/i386/i386/ |
H A D | bpf_jit_machdep.h | 108 /* movl i32,r32 */ 109 #define MOVid(i32, r32) do { \ 111 emitm(&stream, i32, 4); \ 195 /* addl i32,%eax */ 196 #define ADD_EAXi(i32) do { \ 198 emitm(&stream, i32, 4); \ 215 /* subl i32,%eax */ 216 #define SUB_EAXi(i32) do { \ 218 emitm(&stream, i32, 4); \ 251 /* andl i32,r3 [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 124 return CurDAG->getTargetConstant(bitPos, MVT::i32); 148 // i32 where the negative literal is transformed into a positive literal for 152 return CurDAG->getTargetConstant( - Imm, MVT::i32); 165 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); 171 return CurDAG->getTargetConstant(Imm - 1, MVT::i32); 370 if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) { 409 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed; 448 N1.getNode()->getValueType(0) == MVT::i32) { 450 SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32); 451 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MV [all...] |
H A D | HexagonISelLowering.cpp | 107 LocVT = MVT::i32; 108 ValVT = MVT::i32; 116 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 145 LocVT = MVT::i32; 146 ValVT = MVT::i32; 155 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 220 LocVT = MVT::i32; 221 ValVT = MVT::i32; 230 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 247 if (LocVT == MVT::i32 || LocV [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 77 Offset = CurDAG->getTargetConstant(0, MVT::i32); 95 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); 111 Offset = CurDAG->getTargetConstant(0, MVT::i32); 162 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS, 163 CurDAG->getTargetConstant(31, MVT::i32)), 0); 165 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 168 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 172 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 181 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue, 184 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValu [all...] |
H A D | SparcISelLowering.cpp | 131 if (LocVT == MVT::i32 && Offset < 6*8) { 137 // Set the Custom bit if this i32 goes in the high bits of a register. 224 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); 257 RetOps.push_back(DAG.getConstant(8, MVT::i32)); 279 // The custom bit on an i32 return value indicates that it should be passed 281 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 283 DAG.getConstant(32, MVT::i32)); 356 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 357 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 369 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 78 Shift = CurDAG->getTargetConstant(0, MVT::i32); 144 FixedPos = CurDAG->getTargetConstant(64 - FBits, MVT::i32); 174 Dummy = CurDAG->getTargetConstant(0, MVT::i32); 188 Imm = CurDAG->getTargetConstant(Bits, MVT::i32); 213 MOVType = MVT::i32; 221 CurDAG->getTargetConstant(LogicalBits, MVT::i32)); 229 CurDAG->getTargetConstant(UImm16, MVT::i32), 230 CurDAG->getTargetConstant(Shift, MVT::i32)); 234 MVT::i64, MVT::i32, MVT::Other, 237 CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32)); [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 73 /// i32. 75 return CurDAG->getTargetConstant(Imm, MVT::i32); 263 if (PPCLowering.getPointerTy() == MVT::i32) { 286 if (N->getValueType(0) == MVT::i32) 300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 358 if (N->getValueType(0) != MVT::i32) 460 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops); 473 if (LHS.getValueType() == MVT::i32) { 479 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS, 483 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LH [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | SIRegisterInfo.cpp | 51 case MVT::i32: return &AMDGPU::VReg_32RegClass;
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H A D | AMDILISelDAGToDAG.cpp | 101 return CurDAG->getTargetConstant(Imm, MVT::i32); 109 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 110 R2 = CurDAG->getTargetConstant(0, MVT::i32); 113 R2 = CurDAG->getTargetConstant(0, MVT::i32); 120 R2 = CurDAG->getTargetConstant(0, MVT::i32); 176 CurDAG->getTargetConstant(AMDGPU::R600_Reg128RegClassID, MVT::i32), 177 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32), 178 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32), 179 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub2, MVT::i32), 180 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub3, MVT::i32) [all...] |
H A D | R600ISelLowering.cpp | 34 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); 66 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 75 setOperationAction(ISD::ROTL, MVT::i32, Custom); 78 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 80 setOperationAction(ISD::SETCC, MVT::i32, Expand); 84 setOperationAction(ISD::SELECT, MVT::i32, Custom); 91 setOperationAction(ISD::LOAD, MVT::i32, Custom); 99 setOperationAction(ISD::STORE, MVT::i32, Custom); 103 setOperationAction(ISD::LOAD, MVT::i32, Custom); 105 setOperationAction(ISD::FrameIndex, MVT::i32, Custo [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 59 // MBlaze does not have i1 type, so use i32 for 65 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass); 76 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 77 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i32, Expand); 104 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 105 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 109 setOperationAction(ISD::MUL, MVT::i32, Expand); 114 setOperationAction(ISD::MULHS, MVT::i32, Expan [all...] |
H A D | MBlazeISelDAGToDAG.cpp | 88 // getI32Imm - Return a target constant with the specified value, of type i32. 90 return CurDAG->getTargetConstant(Imm, MVT::i32); 106 if (N->getValueType(0) == MVT::i32) 156 Disp = CurDAG->getTargetConstant(imm, MVT::i32); 209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32); 228 SDValue R20Reg = CurDAG->getRegister(MBlaze::R20, MVT::i32); 235 SDValue GPReg = CurDAG->getRegister(MBlaze::R15, MVT::i32); 240 MVT::i32, MVT::Other, Ops), 0);
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/freebsd-10.0-release/sys/amd64/amd64/ |
H A D | bpf_jit_machdep.h | 133 /* movl i32,r32 */ 134 #define MOVid(i32, r32) do { \ 136 emitm(&stream, i32, 4); \ 250 /* addl i32,%eax */ 251 #define ADD_EAXi(i32) do { \ 253 emitm(&stream, i32, 4); \ 270 /* subl i32,%eax */ 271 #define SUB_EAXi(i32) do { \ 273 emitm(&stream, i32, 4); \ 306 /* andl i32,r3 [all...] |
/freebsd-10.0-release/tools/tools/shlib-compat/test/libtest3/ |
H A D | test.c | 37 typedef int i32; typedef 43 int32_t func5(i32 a, void *b, struct s2 *s);
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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 34 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 78 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 79 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 80 setOperationAction(ISD::MULHS, MVT::i32, Custom); 81 setOperationAction(ISD::MULHU, MVT::i32, Custom); 92 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 93 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 97 setOperationAction(ISD::LOAD, MVT::i32, Custom); 98 setOperationAction(ISD::STORE, MVT::i32, Custom); 118 case MVT::i32 [all...] |
H A D | MipsISelLowering.cpp | 215 // Mips does not have i1 type, so use i32 for 233 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 237 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 238 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 239 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 240 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 241 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 244 setOperationAction(ISD::SELECT, MVT::i32, Custom); 271 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 272 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custo [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 235 case MVT::i32: 264 case MVT::i32: 294 case MVT::i32: 317 case MVT::i32: 346 case MVT::i32: 369 case MVT::i32: 476 case MVT::i32: 500 case MVT::i32: 530 case MVT::i32: 554 case MVT::i32 [all...] |
H A D | NVPTXISelLowering.cpp | 95 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); 107 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 123 setOperationAction(ISD::ROTL, MVT::i32, Legal); 124 setOperationAction(ISD::ROTR, MVT::i32, Legal); 126 setOperationAction(ISD::ROTL, MVT::i32, Expand); 127 setOperationAction(ISD::ROTR, MVT::i32, Expand); 135 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 143 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 162 setTruncStoreAction(MVT::i32, MV [all...] |
H A D | NVPTXISelLowering.h | 138 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 146 EVT = MVT::i32) const; 147 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT = MVT::i32) const;
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