Searched refs:SRA (Results 1 - 25 of 37) sorted by relevance

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/freebsd-10.0-release/contrib/telnet/libtelnet/
H A Dauth-proto.h102 #ifdef SRA
H A Dauth.c172 #ifdef SRA
H A Dsra.c35 #ifdef SRA
143 printf("Trying SRA secure login:\r\n");
153 /* server received an IS -- could be SRA KEY, USER, or PASS */
169 printf("SRA user rejected for bad PKB\r\n");
218 printf("SRA user accepted\r\n");
229 printf("SRA user failed\r\n");
236 printf("Unknown SRA option %d\r\n", data[-1]);
244 /* client received REPLY -- could be SRA KEY, CONTINUE, ACCEPT, or REJECT */
260 printf("SRA user rejected for bad PKB\r\n");
302 printf("[ SRA logi
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/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h28 case ISD::SRA: return ARM_AM::asr;
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp181 { ISD::SRA, MVT::v4i32, 1 },
184 { ISD::SRA, MVT::v8i32, 1 },
196 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
197 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
198 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
223 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
224 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
225 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
257 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
258 { ISD::SRA, MV
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H A DX86ISelLowering.cpp806 setOperationAction(ISD::SRA, VT, Expand);
1063 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1064 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1074 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1140 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1141 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1324 setTargetDAGCombine(ISD::SRA);
7926 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7936 Tmp3 = DAG.getNode(isSRA ? ISD::SRA
11541 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG); local
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/freebsd-10.0-release/crypto/heimdal/appl/telnet/libtelnet/
H A Dauth-proto.h91 #ifdef SRA
H A Dauth.c119 #ifdef SRA
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h318 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
382 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon2425
H A DMSP430ISelLowering.cpp95 setOperationAction(ISD::SRA, MVT::i8, Custom);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
191 case ISD::SRA: return LowerShifts(Op, DAG);
637 case ISD::SRA:
638 return DAG.getNode(MSP430ISD::SRA, dl,
857 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1033 case MSP430ISD::SRA: return "MSP430ISD::SRA";
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
561 return DAG.getNode(ISD::SRA, N->getDebugLoc(), Res.getValueType(), Res, Amt);
796 case ISD::SRA:
1151 case ISD::SRA:
1319 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1321 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1324 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1326 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1330 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1338 Hi = DAG.getNode(ISD::SRA, D
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H A DLegalizeVectorOps.cpp18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
64 // Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
209 case ISD::SRA:
485 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
635 // Make sure that the SRA and SHL instructions are available.
636 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
649 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
H A DDAGCombiner.cpp880 if (Opc == ISD::SRA)
1122 case ISD::SRA: return visitSRA(N);
1205 case ISD::SRA:
1895 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1907 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, local
1913 return SRA;
1915 AddToWorkList(SRA.getNode());
1917 DAG.getConstant(0, VT), SRA);
2096 return DAG.getNode(ISD::SRA,
3815 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, local
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H A DFastISel.cpp414 ISDOpcode = ISD::SRA;
999 return SelectBinaryOp(I, ISD::SRA);
1168 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
H A DSelectionDAGBuilder.h491 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
H A DSelectionDAGDumper.cpp172 case ISD::SRA: return "sra";
H A DSelectionDAG.cpp1844 case ISD::SRA:
2125 /// information. For example, immediately after an "SRA X, 2", we know that
2164 case ISD::SRA:
2166 // SRA X, C -> adds C sign bits.
2773 case ISD::SRA:
2911 case ISD::SRA:
3172 case ISD::SRA:
3230 case ISD::SRA:
6145 case ISD::SRA:
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h100 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp57 setTargetDAGCombine(ISD::SRA);
437 case ISD::SRA:
H A DMipsISelLowering.cpp571 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
1112 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1337 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1892 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1896 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DAMDILISelLowering.cpp352 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
419 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
H A DR600ISelLowering.cpp55 setOperationAction(ISD::SRA, MVT::v4i32, Expand);
56 setOperationAction(ISD::SRA, MVT::v2i32, Expand);
/freebsd-10.0-release/contrib/llvm/lib/TableGen/
H A DRecord.cpp940 case SRA:
951 case SRA: Result = LHSv >> RHSv; break;
977 case SRA: Result = "!sra"; break;
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp122 case 0x01: return MBlaze::SRA;

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