/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 44 unsigned Opc = MI->getOpcode(); local 46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || 47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || 48 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || 49 (Opc 69 unsigned Opc = MI->getOpcode(); local 89 unsigned Opc = 0, ZeroReg = 0; local 182 unsigned Opc = 0; local 215 unsigned Opc = 0; local [all...] |
H A D | Mips16InstrInfo.cpp | 72 unsigned Opc = 0; local 76 Opc = Mips::MoveR3216; 79 Opc = Mips::Move32R16; 82 Opc = Mips::Mfhi16, SrcReg = 0; 86 Opc = Mips::Mflo16, SrcReg = 0; 89 assert(Opc && "Cannot copy registers"); 91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 108 unsigned Opc = 0; local 110 Opc = Mips::SwRxSpImmX16; 111 assert(Opc 123 unsigned Opc = 0; local [all...] |
H A D | MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst 21 Inst(unsigned Opc, unsigned ImmOpnd);
|
H A D | Mips16InstrInfo.h | 67 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; 105 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; 108 unsigned Opc) const;
|
H A D | MipsSEInstrInfo.h | 68 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; 82 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; 85 unsigned Opc) const;
|
H A D | MipsInstrInfo.h | 84 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const = 0; 126 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const = 0; 128 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
|
H A D | Mips16ISelDAGToDAG.h | 26 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, DebugLoc DL,
|
H A D | MipsAnalyzeImmediate.cpp | 15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {} 88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || 89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) 100 Seq[0].Opc = LUi;
|
H A D | Mips16ISelDAGToDAG.cpp | 45 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty, argument 48 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0), 253 unsigned Opc = InFlag.getOpcode(); (void)Opc; local 254 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || 255 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
H A D | MipsInstrInfo.cpp | 77 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, argument 80 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch"); 86 Cond.push_back(MachineOperand::CreateImm(Opc)); 107 unsigned Opc = Cond[0].getImm(); local 108 const MCInstrDesc &MCID = get(Opc);
|
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMInstrInfo.h | 33 // Return the non-pre/post incrementing version of 'Opc'. Return 0 35 unsigned getUnindexedOpcode(unsigned Opc) const;
|
H A D | ARMBaseInstrInfo.h | 41 // Return the non-pre/post incrementing version of 'Opc'. Return 0 43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 349 bool isUncondBranchOpcode(int Opc) { argument 350 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 354 bool isCondBranchOpcode(int Opc) { argument 355 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc 359 isJumpTableBranchOpcode(int Opc) argument 365 isIndirectBranchOpcode(int Opc) argument [all...] |
H A D | ARMInstrInfo.cpp | 52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { 53 switch (Opc) { 122 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? local 126 TII.get(Opc), GlobalBaseReg) 128 if (Opc == ARM::LDRcp)
|
H A D | Thumb1InstrInfo.h | 32 // Return the non-pre/post incrementing version of 'Opc'. Return 0 34 unsigned getUnindexedOpcode(unsigned Opc) const;
|
H A D | Thumb2InstrInfo.h | 33 // Return the non-pre/post incrementing version of 'Opc'. Return 0 35 unsigned getUnindexedOpcode(unsigned Opc) const;
|
H A D | ARMISelDAGToDAG.cpp | 113 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc); 116 SDValue &Offset, SDValue &Opc); 118 SDValue &Opc) { 119 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE; 123 SDValue &Opc) { 124 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP; 128 SDValue &Opc) { 129 SelectAddrMode2Worker(N, Base, Offset, Opc); 130 // return SelectAddrMode2ShOp(N, Base, Offset, Opc); 136 SDValue &Offset, SDValue &Opc); 117 SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 122 SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 127 SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 308 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument 474 SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) argument 497 SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) argument 575 SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 672 SelectAddrMode2Worker(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 808 SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 844 SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 864 SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 889 SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument 937 SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument 1238 SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, SDValue &Opc) argument 1643 getVLDSTRegisterUpdateOpcode(unsigned Opc) argument 1745 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local 1895 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local 2062 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local 2126 unsigned Opc = Opcodes[OpcodeIndex]; local 2166 SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc) argument 2204 unsigned Opc = isSigned local 2289 unsigned Opc = 0; local 2334 unsigned Opc = 0; local 2365 unsigned Opc = 0; local 2461 unsigned Opc = 0; local 2527 SelectAtomic64(SDNode *Node, unsigned Opc) argument 2628 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? local 2697 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) local 2817 unsigned Opc = Subtarget->isThumb() ? local 2846 unsigned Opc = 0; local 2866 unsigned Opc = 0; local 2886 unsigned Opc = 0; local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 60 static bool IsConditionalBranch(int Opc) { argument 61 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f) 62 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t); 66 static bool IsUnconditionalJump(int Opc) { argument 67 return (Opc == Hexagon::JMP); 113 int Opc = MI->getOpcode(); local 114 if (IsConditionalBranch(Opc)) {
|
/freebsd-10.0-release/contrib/llvm/include/llvm/IR/ |
H A D | InstrTypes.h | 194 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument 196 BinaryOperator *BO = Create(Opc, V1, V2, Name); 200 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument 202 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB); 206 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument 208 BinaryOperator *BO = Create(Opc, V1, V2, Name, I); 213 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument 215 BinaryOperator *BO = Create(Opc, V1, V2, Name); 219 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument 221 BinaryOperator *BO = Create(Opc, V 225 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument 232 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = �) argument 238 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument 244 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 90 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 185 unsigned Opc = 0; local 191 Opc = X86::MOV8rm; 195 Opc = X86::MOV16rm; 199 Opc = X86::MOV32rm; 204 Opc = X86::MOV64rm; 209 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; 212 Opc = X86::LD_Fp32m; 218 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; 221 Opc 243 unsigned Opc = 0; local 294 unsigned Opc = 0; local 328 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument 543 unsigned Opc = 0; local 1362 unsigned Opc = 0; local 1632 unsigned Opc = X86::SETBr; local 2160 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; local 2246 unsigned Opc = 0; local 2354 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; local 2368 unsigned Opc = 0; local [all...] |
H A D | X86FrameLowering.cpp | 107 unsigned Opc = MBBI->getOpcode(); local 108 switch (Opc) { 152 unsigned Opc; 154 Opc = getLEArOpcode(IsLP64); 156 Opc = isSub 171 Opc = isSub 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) 186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), 189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 209 unsigned Opc [all...] |
H A D | X86ISelDAGToDAG.cpp | 189 SDNode *SelectGather(SDNode *N, unsigned Opc); 190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 1493 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { argument 1505 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), 1727 unsigned Opc = 0; local 1732 Opc = AtomicOpcTbl[Op][ConstantI8]; 1734 Opc = AtomicOpcTbl[Op][I8]; 1739 Opc = AtomicOpcTbl[Op][SextConstantI16]; 1741 Opc = AtomicOpcTbl[Op][ConstantI16]; 1743 Opc 1849 isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc, SDValue StoredVal, SelectionDAG *CurDAG, LoadSDNode* &LoadNode, SDValue &InputChain) argument 1934 getFusedLdStOpcode(EVT &LdVT, unsigned Opc) argument 1952 SelectGather(SDNode *Node, unsigned Opc) argument 1983 unsigned Opc, MOpc; local 2017 unsigned Opc; local 2061 unsigned Opc; local 2650 unsigned Opc = StoredVal->getOpcode(); local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.h | 144 inline static bool isUncondBranchOpcode(int Opc) { argument 145 switch (Opc) { 155 inline static bool isCondBranchOpcode(int Opc) { argument 156 switch (Opc) {
|
H A D | MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode(); local 102 if (Opc != ISD::Constant) 213 unsigned Opc = MBlaze::ADDIK; local 215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm); 216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
/freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
H A D | FixedLenDecoderEmitter.cpp | 421 void SingletonExists(unsigned Opc) const; 439 unsigned Opc) const; 441 bool doesOpcodeNeedPredicate(unsigned Opc) const; 444 unsigned Opc) const; 447 unsigned Opc) const; 451 unsigned Opc) const; 460 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc) const; 461 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc) const; 819 unsigned Opc = decodeULEB128(Buffer); 831 << NumberedInstructions->at(Opc) [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 465 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; local 466 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); 477 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 482 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 487 assert(!(ImmS == 31 && !SF && Opc != BFM) 489 assert(!(ImmS == 63 && SF && Opc != BFM) 493 if (Opc == SBFM && ImmR == 0) { 496 } else if (Opc == UBFM && ImmR == 0) { 500 if (Opc == UBFM) { 517 switch (Opc) { 581 unsigned Opc = fieldFromInstruction(Insn, 30, 2); local 742 unsigned Opc = fieldFromInstruction(Insn, 22, 2); local [all...] |