/freebsd-10.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCInstrAnalysis.h | 31 virtual bool isBranch(const MCInst &Inst) const { 32 return Info->get(Inst.getOpcode()).isBranch(); 35 virtual bool isConditionalBranch(const MCInst &Inst) const { 36 return Info->get(Inst.getOpcode()).isConditionalBranch(); 39 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 40 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 43 virtual bool isIndirectBranch(const MCInst &Inst) const { 44 return Info->get(Inst.getOpcode()).isIndirectBranch(); 47 virtual bool isCall(const MCInst &Inst) const { 48 return Info->get(Inst [all...] |
H A D | MCInstBuilder.h | 23 MCInst Inst; member in class:llvm::MCInstBuilder 28 Inst.setOpcode(Opcode); 33 Inst.addOperand(MCOperand::CreateReg(Reg)); 39 Inst.addOperand(MCOperand::CreateImm(Val)); 45 Inst.addOperand(MCOperand::CreateFPImm(Val)); 51 Inst.addOperand(MCOperand::CreateExpr(Val)); 57 Inst.addOperand(MCOperand::CreateInst(Val)); 62 return Inst;
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/freebsd-10.0-release/contrib/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 13 uint64_t MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 15 if (Inst.getNumOperands() == 0 || 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 19 int64_t Imm = Inst.getOperand(0).getImm();
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/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 92 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 97 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 100 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, 103 static DecodeStatus Decode2RInstruction(MCInst &Inst, 108 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, 113 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 118 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 123 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 128 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 210 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 222 DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 234 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 245 DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 286 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 356 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 369 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 382 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 395 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 409 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 422 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 435 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 449 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 520 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 534 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 548 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 561 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 574 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 587 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 600 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 614 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 629 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 643 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 657 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 677 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 691 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 711 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 730 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsDirectObjLower.h | 23 void LowerLargeShift(MCInst &Inst); 24 void LowerDextDins(MCInst &Inst);
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H A D | MipsDirectObjLower.cpp | 23 void Mips::LowerLargeShift(MCInst& Inst) { argument 25 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!"); 26 assert(Inst.getOperand(2).isImm()); 28 int64_t Shift = Inst.getOperand(2).getImm(); 34 Inst.getOperand(2).setImm(Shift); 36 switch (Inst.getOpcode()) { 41 Inst.setOpcode(Mips::DSLL32); 44 Inst.setOpcode(Mips::DSRL32); 47 Inst.setOpcode(Mips::DSRA32);
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/freebsd-10.0-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | EarlyCSE.cpp | 50 Instruction *Inst; member in struct:__anon2628::SimpleValue 52 SimpleValue(Instruction *I) : Inst(I) { 53 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!"); 57 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() || 58 Inst == DenseMapInfo<Instruction*>::getTombstoneKey(); 61 static bool canHandle(Instruction *Inst) { argument 63 if (CallInst *CI = dyn_cast<CallInst>(Inst)) 65 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) || 66 isa<GetElementPtrInst>(Inst) || is 93 Instruction *Inst = Val.Inst; local 198 Instruction *Inst; member in struct:__anon2629::CallValue 209 canHandle(Instruction *Inst) argument 240 Instruction *Inst = Val.Inst; local 432 Instruction *Inst = I++; local 537 << *Inst << '\\n'); local [all...] |
H A D | Sink.cpp | 58 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const; 59 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const; 74 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument 80 for (Value::use_iterator I = Inst->use_begin(), 81 E = Inst->use_end(); I != E; ++I) { 136 Instruction *Inst = I; // The instruction to sink. local 144 if (isa<DbgInfoIntrinsic>(Inst)) 147 if (SinkInstruction(Inst, Stores)) 156 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument 159 if (Inst 180 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const argument 219 SinkInstruction(Instruction *Inst, SmallPtrSet<Instruction *, 8> &Stores) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 159 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 171 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 175 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigne 900 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 911 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 923 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 930 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 960 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 977 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 998 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1008 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1016 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1031 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1051 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1072 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1084 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1098 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1107 DecodeSOImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1116 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1153 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1188 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1223 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1240 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1259 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1286 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1431 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1536 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1580 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1771 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1800 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1885 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1925 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1967 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1991 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2018 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2046 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2066 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2085 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2091 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2118 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2144 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2161 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2435 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2706 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2753 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2801 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2836 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2891 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2936 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2955 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2961 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2967 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2973 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2979 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3015 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3039 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3047 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3055 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3063 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3078 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3092 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3102 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3110 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3127 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3182 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3196 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3211 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument 3226 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3239 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3270 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3300 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3315 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3326 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3351 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3362 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3375 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3399 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3409 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3425 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3467 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3499 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3507 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3530 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3539 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3546 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3569 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3596 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3621 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3649 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3674 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3699 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3766 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3832 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3899 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3963 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4033 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4097 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4178 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4250 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4276 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4302 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4324 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4361 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4395 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument 4410 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument 4421 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4448 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4476 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4504 DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4513 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4540 DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument [all...] |
/freebsd-10.0-release/contrib/llvm/tools/llvm-objdump/ |
H A D | MCFunction.cpp | 55 MCInst Inst; local 56 if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut, nulls())){ 57 Instructions.push_back(MCDecodedInst(Index, Size, Inst)); 58 if (Ana->isBranch(Inst)) { 59 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size); 72 } else if (Ana->isReturn(Inst)) { 76 } else if (Ana->isCall(Inst)) { 77 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size); 116 const MCDecodedInst &Inst = BB.getInsts().back(); local 118 if (Ana->isBranch(Inst [all...] |
H A D | MCFunction.h | 35 MCInst Inst; member in struct:llvm::MCDecodedInst 38 MCDecodedInst(uint64_t Address, uint64_t Size, MCInst Inst) argument 39 : Address(Address), Size(Size), Inst(Inst) {} 61 void addInst(const MCDecodedInst &Inst) { Insts.push_back(Inst); } argument
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/freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
H A D | InstrInfoEmitter.cpp | 48 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 56 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 73 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument 76 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { 85 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; 89 OperandList.push_back(Inst.Operands[i]); 91 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { 92 OperandList.push_back(Inst.Operands[i]); 122 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) 127 if (Inst 206 Record *Inst = (*II)->TheDef; local 298 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 66 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 78 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 80 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 82 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 84 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 86 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 89 static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst, 240 DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 251 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 261 DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 273 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 284 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 295 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 307 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 318 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 330 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 341 DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 351 DecodeAddrRegExtendOperand(llvm::MCInst &Inst, unsigned OptionHiS, uint64_t Address, const void *Decoder) argument 364 DecodeBitfield32ImmOperand(llvm::MCInst &Inst, unsigned Imm6Bits, uint64_t Address, const void *Decoder) argument 377 DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, unsigned Imm6Bits, uint64_t Address, const void *Decoder) argument 389 DecodeFPZeroOperand(llvm::MCInst &Inst, unsigned RmBits, uint64_t Address, const void *Decoder) argument 402 DecodeMoveWideImmOperand(llvm::MCInst &Inst, unsigned FullImm, uint64_t Address, const void *Decoder) argument 417 DecodeLogicalImmOperand(llvm::MCInst &Inst, unsigned Bits, uint64_t Address, const void *Decoder) argument 430 DecodeRegExtendOperand(llvm::MCInst &Inst, unsigned ShiftAmount, uint64_t Address, const void *Decoder) argument 442 Decode32BitShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, uint64_t Address, const void *Decoder) argument 454 DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 546 DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 570 DecodeLDSTPairInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 654 DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument 690 DecodeNamedImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 705 DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 718 DecodeMRSOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 726 DecodeMSROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 734 DecodeSingleIndexedInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 91 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, 96 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 101 static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst, 106 static DecodeStatus DecodeDSPRegsRegisterClass(MCInst &Inst, 111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 126 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 131 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 136 static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, 340 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 349 DecodeCPU64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 362 DecodeCPURegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 373 DecodeDSPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 380 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 392 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 404 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 412 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 434 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 453 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 464 DecodeCondCode(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 473 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 486 DecodeHWRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 497 DecodeACRegsDSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 509 DecodeHIRegsDSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 521 DecodeLORegsDSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 533 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 543 DecodeBC1(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 553 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 564 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 572 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 583 DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 188 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 189 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 190 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 192 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 194 void cvtLdWriteBackRegAddrMode2(MCInst &Inst, 196 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 198 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 200 void cvtStWriteBackRegAddrMode2(MCInst &Inst, 202 void cvtStWriteBackRegAddrMode3(MCInst &Inst, 204 void cvtLdExtTWriteBackImm(MCInst &Inst, 1436 addExpr(MCInst &Inst, const MCExpr *Expr) const argument 1446 addCondCodeOperands(MCInst &Inst, unsigned N) const argument 1453 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument 1458 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument 1463 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument 1468 addITMaskOperands(MCInst &Inst, unsigned N) const argument 1473 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument 1478 addCCOutOperands(MCInst &Inst, unsigned N) const argument 1483 addRegOperands(MCInst &Inst, unsigned N) const argument 1488 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument 1498 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument 1509 addShifterImmOperands(MCInst &Inst, unsigned N) const argument 1515 addRegListOperands(MCInst &Inst, unsigned N) const argument 1523 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument 1527 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument 1531 addRotImmOperands(MCInst &Inst, unsigned N) const argument 1537 addBitfieldOperands(MCInst &Inst, unsigned N) const argument 1548 addImmOperands(MCInst &Inst, unsigned N) const argument 1553 addFBits16Operands(MCInst &Inst, unsigned N) const argument 1559 addFBits32Operands(MCInst &Inst, unsigned N) const argument 1565 addFPImmOperands(MCInst &Inst, unsigned N) const argument 1572 addImm8s4Operands(MCInst &Inst, unsigned N) const argument 1580 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument 1588 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument 1596 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument 1604 addImm1_16Operands(MCInst &Inst, unsigned N) const argument 1612 addImm1_32Operands(MCInst &Inst, unsigned N) const argument 1620 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument 1629 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument 1638 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument 1646 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument 1654 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument 1662 addARMSOImmNotOperands(MCInst &Inst, unsigned N) const argument 1670 addARMSOImmNegOperands(MCInst &Inst, unsigned N) const argument 1678 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument 1683 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument 1688 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument 1696 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument 1712 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument 1718 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument 1936 addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const argument 1943 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument 1950 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument 1957 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument 1968 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument 1980 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument 1986 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument 1997 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument 2002 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument 2007 addVecListOperands(MCInst &Inst, unsigned N) const argument 2012 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument 2018 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument 2023 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument 2028 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument 2033 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument 2041 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument 2053 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument 2067 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument 2081 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument 2095 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument 3933 cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3950 cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3967 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3982 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3995 cvtLdWriteBackRegAddrMode2(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4010 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4026 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4039 cvtStWriteBackRegAddrMode2(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4052 cvtStWriteBackRegAddrMode3(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4065 cvtLdExtTWriteBackImm(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4083 cvtLdExtTWriteBackReg(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4101 cvtStExtTWriteBackImm(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4119 cvtStExtTWriteBackReg(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4137 cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4154 cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4171 cvtLdWriteBackRegAddrMode3(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4184 cvtThumbMultiply(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4201 cvtVLDwbFixed(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4214 cvtVLDwbRegister(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4229 cvtVSTwbFixed(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4242 cvtVSTwbRegister(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5261 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument 5277 listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) argument 5298 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5731 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 7502 checkTargetMatchPredicate(MCInst &Inst) argument 7550 MCInst Inst; local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.h | 19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate 21 Inst(unsigned Opc, unsigned ImmOpnd); 23 typedef SmallVector<Inst, 7 > InstSeq; 33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
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/freebsd-10.0-release/contrib/llvm/lib/Transforms/ObjCARC/ |
H A D | ObjCARCExpand.cpp | 98 Instruction *Inst = &*I; local 100 DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n"); 102 switch (GetBasicInstructionClass(Inst)) { 114 Value *Value = cast<CallInst>(Inst)->getArgOperand(0); 115 DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst << "\n" 117 Inst->replaceAllUsesWith(Value);
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H A D | DependencyAnalysis.cpp | 35 llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, argument 48 ImmutableCallSite CS = static_cast<const Value *>(Inst); 72 llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, argument 80 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) { 86 } else if (ImmutableCallSite CS = static_cast<const Value *>(Inst)) { 95 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) { 105 for (User::const_op_iterator OI = Inst->op_begin(), OE = Inst->op_end(); 114 /// Test if there can be dependencies on Inst through Arg. This function only 117 llvm::objcarc::Depends(DependenceKind Flavor, Instruction *Inst, argument 237 Instruction *Inst = --LocalStartPos; local [all...] |
H A D | DependencyAnalysis.h | 61 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg, 67 CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA, 73 CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
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H A D | ObjCARCAPElim.cpp | 98 Instruction *Inst = I++; local 99 switch (GetBasicInstructionClass(Inst)) { 101 Push = Inst; 106 if (Push && cast<CallInst>(Inst)->getArgOperand(0) == Push) { 110 " Pop: " << *Inst << "\n" 112 Inst->eraseFromParent(); 118 if (MayAutorelease(ImmutableCallSite(Inst)))
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/freebsd-10.0-release/contrib/llvm/lib/Analysis/ |
H A D | PHITransAddr.cpp | 25 static bool CanPHITrans(Instruction *Inst) { argument 26 if (isa<PHINode>(Inst) || 27 isa<GetElementPtrInst>(Inst)) 30 if (isa<CastInst>(Inst) && 31 isSafeToSpeculativelyExecute(Inst)) 34 if (Inst->getOpcode() == Instruction::Add && 35 isa<ConstantInt>(Inst->getOperand(1))) 118 Instruction *Inst = dyn_cast<Instruction>(Addr); local 119 return Inst == 0 || CanPHITrans(Inst); 149 Instruction *Inst = dyn_cast<Instruction>(V); local [all...] |
H A D | MemDepPrinter.cpp | 102 Instruction *Inst = &*I; local 104 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory()) 107 MemDepResult Res = MDA.getDependency(Inst); 109 Deps[Inst].insert(std::make_pair(getInstTypePair(Res), 111 } else if (CallSite CS = cast<Value>(Inst)) { 115 DepSet &InstDeps = Deps[Inst]; 123 if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) { 126 Deps[Inst].insert(std::make_pair(getInstTypePair(0, Unknown), 132 } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) { 162 const Instruction *Inst = &*I; local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/MBlaze/MCTargetDesc/ |
H A D | MBlazeAsmBackend.cpp | 53 bool mayNeedRelaxation(const MCInst &Inst) const; 60 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 78 bool MBlazeAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 79 if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode()) 83 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) 84 hasExprOrImm |= Inst.getOperand(i).isExpr(); 101 void MBlazeAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { argument 102 Res = Inst; 103 Res.setOpcode(getRelaxedOpcode(Inst [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 124 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 125 if (Inst.getOpcode() == AArch64::Bcc 126 && Inst.getOperand(0).getImm() == A64CC::AL) 128 return MCInstrAnalysis::isUnconditionalBranch(Inst); 131 virtual bool isConditionalBranch(const MCInst &Inst) const { 132 if (Inst.getOpcode() == AArch64::Bcc 133 && Inst.getOperand(0).getImm() == A64CC::AL) 135 return MCInstrAnalysis::isConditionalBranch(Inst); 138 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 140 unsigned LblOperand = Inst [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 139 void ProcessInstruction(MCInst &Inst, 273 void addRegOperands(MCInst &Inst, unsigned N) const { argument 277 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { argument 279 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); 282 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { argument 284 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); 287 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { argument 289 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); 292 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { argument 294 Inst 297 addRegGxRCOperands(MCInst &Inst, unsigned N) const argument 304 addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const argument 311 addRegF4RCOperands(MCInst &Inst, unsigned N) const argument 316 addRegF8RCOperands(MCInst &Inst, unsigned N) const argument 321 addRegVRRCOperands(MCInst &Inst, unsigned N) const argument 326 addRegCRBITRCOperands(MCInst &Inst, unsigned N) const argument 331 addRegCRRCOperands(MCInst &Inst, unsigned N) const argument 336 addCRBitMaskOperands(MCInst &Inst, unsigned N) const argument 341 addImmOperands(MCInst &Inst, unsigned N) const argument 349 addDispRIOperands(MCInst &Inst, unsigned N) const argument 357 addDispRIXOperands(MCInst &Inst, unsigned N) const argument 420 ProcessInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 477 MCInst Inst; local [all...] |