Searched refs:FSUB (Results 1 - 24 of 24) sorted by relevance

/freebsd-10.0-release/bin/pax/
H A Doptions.c99 FSUB fsub[] = {
192 FSUB tmp;
369 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub,
370 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) {
376 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i)
1019 FSUB tmp;
1185 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub,
1186 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frm
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H A Dpax.h72 typedef struct fsub FSUB; typedef in typeref:struct:fsub
H A Dextern.h183 extern FSUB fsub[];
206 extern FSUB *frmt;
H A Dpax.c74 FSUB *frmt = NULL; /* archive format type */
H A Dar_subs.c567 FSUB *orgfrmt;
/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h234 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
201 case ISD::FSUB:
735 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
737 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
H A DSelectionDAGBuilder.cpp2635 visitBinary(I, ISD::FSUB);
3710 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3826 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3843 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3849 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3868 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3874 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3880 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3920 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3937 SDValue t3 = DAG.getNode(ISD::FSUB, d
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H A DSelectionDAGDumper.cpp177 case ISD::FSUB: return "fsub";
H A DLegalizeFloatTypes.cpp93 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
822 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1376 DAG.getNode(ISD::FSUB, dl,
H A DSelectionDAG.cpp2652 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB)
2653 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2861 case ISD::FSUB:
2875 } else if (Opcode == ISD::FSUB) {
3122 case ISD::FSUB:
3169 case ISD::FSUB:
3208 case ISD::FSUB:
H A DDAGCombiner.cpp422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
432 case ISD::FSUB:
485 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
490 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
494 case ISD::FSUB:
504 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
1141 case ISD::FSUB: return visitFSUB(N);
5862 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
5864 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5867 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, V
[all...]
H A DLegalizeVectorTypes.cpp104 case ISD::FSUB:
557 case ISD::FSUB:
1446 case ISD::FSUB:
H A DLegalizeDAG.cpp2265 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2303 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2921 DAG.getNode(ISD::FSUB, dl, VT,
3125 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3282 case ISD::FSUB: {
H A DFastISel.cpp977 return SelectBinaryOp(I, ISD::FSUB);
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp171 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
H A DR600ISelLowering.cpp40 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
69 setOperationAction(ISD::FSUB, MVT::f32, Expand);
H A DAMDILISelLowering.cpp178 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4733 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4743 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4749 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4755 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4761 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6739 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6802 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6813 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1197 case FSub: return ISD::FSUB;
/freebsd-10.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp217 setOperationAction(ISD::FSUB, MVT::f128, Custom);
2383 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1834 case ISD::FSUB:
2765 return SelectBinaryFPOp(I, ISD::FSUB);
H A DARMISelLowering.cpp475 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
8052 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8055 Opcode != ISD::FADD && Opcode != ISD::FSUB)
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp766 setOperationAction(ISD::FSUB, VT, Expand);
879 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
1093 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1106 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1330 setTargetDAGCombine(ISD::FSUB);
8103 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8154 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12534 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17836 case ISD::FSUB
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