/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 86 static inline unsigned rotr32(unsigned Val, unsigned Amt) { argument 87 assert(Amt < 32 && "Invalid rotate amount"); 88 return (Val >> Amt) | (Val << ((32-Amt)&31)); 93 static inline unsigned rotl32(unsigned Val, unsigned Amt) { argument 94 assert(Amt < 32 && "Invalid rotate amount"); 95 return (Val << Amt) | (Val >> ((32-Amt)&31));
|
/freebsd-10.0-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/ |
H A D | BasicValueFactory.cpp | 178 uint64_t Amt = V2.getZExtValue(); 180 if (Amt > V1.getBitWidth()) 183 return &getValue( V1.operator<<( (unsigned) Amt )); 196 uint64_t Amt = V2.getZExtValue(); 198 if (Amt > V1.getBitWidth()) 201 return &getValue( V1.operator>>( (unsigned) Amt ));
|
/freebsd-10.0-release/contrib/llvm/include/llvm/ADT/ |
H A D | APSInt.h | 114 APSInt operator>>(unsigned Amt) const { 115 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false); 117 APSInt& operator>>=(unsigned Amt) { argument 118 *this = *this >> Amt; 158 APSInt& operator<<=(unsigned Amt) { argument 159 *this = *this << Amt;
|
H A D | APInt.h | 849 APInt sshl_ov(unsigned Amt, bool &Overflow) const;
|
/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Analysis/ |
H A D | FormatString.cpp | 82 const OptionalAmount &Amt = ParseAmount(I, E); local 84 if (Amt.getHowSpecified() == OptionalAmount::NotSpecified) { 95 assert(Amt.getHowSpecified() == OptionalAmount::Constant); 101 if (Amt.getConstantAmount() == 0) { 109 return OptionalAmount(OptionalAmount::Arg, Amt.getConstantAmount() - 1, 132 const OptionalAmount Amt = local 136 if (Amt.isInvalid()) 138 CS.setFieldWidth(Amt); 151 const OptionalAmount &Amt = ParseAmount(I, E); local 159 if (Amt [all...] |
H A D | ScanfFormatString.cpp | 124 const OptionalAmount &Amt = clang::analyze_format_string::ParseAmount(I, E); local 125 if (Amt.getHowSpecified() != OptionalAmount::NotSpecified) { 126 assert(Amt.getHowSpecified() == OptionalAmount::Constant); 127 FS.setFieldWidth(Amt);
|
H A D | PrintfFormatString.cpp | 43 const OptionalAmount Amt = ParsePositionAmount(H, Start, Beg, E, local 45 if (Amt.isInvalid()) 47 FS.setPrecision(Amt);
|
/freebsd-10.0-release/contrib/llvm/include/llvm/IR/ |
H A D | BasicBlock.h | 286 /// referencing this BasicBlock by \p Amt. 290 void AdjustBlockAddressRefCount(int Amt) { argument 291 setValueSubclassData(getSubclassDataFromValue()+Amt);
|
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 535 SDValue Amt = N->getOperand(1); local 536 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; 537 return DAG.getNode(ISD::SHL, N->getDebugLoc(), Res.getValueType(), Res, Amt); 559 SDValue Amt = N->getOperand(1); local 560 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) 567 SDValue Amt = N->getOperand(1); local 1255 ExpandShiftByConstant(SDNode *N, unsigned Amt, SDValue &Lo, SDValue &Hi) argument 1348 SDValue Amt = N->getOperand(1); local 1436 SDValue Amt = N->getOperand(1); local [all...] |
H A D | LegalizeTypes.h | 338 void ExpandShiftByConstant(SDNode *N, unsigned Amt,
|
H A D | DAGCombiner.cpp | 251 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 3496 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { argument 3766 SDValue Amt = DAG.getConstant(ShiftAmt, local 3769 N0.getOperand(0), Amt); 3812 SDValue Amt = local 3816 N0.getOperand(0).getOperand(0), Amt); 5052 unsigned Amt = RHSC->getZExtValue(); local 5055 if (Amt >= Mask.getBitWidth()) break; 5056 APInt NewMask = Mask << Amt;
|
H A D | TargetLowering.cpp | 2450 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType())); local 2451 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
|
/freebsd-10.0-release/contrib/llvm/tools/clang/include/clang/Analysis/Analyses/ |
H A D | FormatString.h | 359 void setFieldWidth(const OptionalAmount &Amt) { argument 360 FieldWidth = Amt; 467 void setPrecision(const OptionalAmount &Amt) { argument 468 Precision = Amt;
|
/freebsd-10.0-release/contrib/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCasts.cpp | 126 Value *Amt = 0; local 128 Amt = NumElements; 130 Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale); 132 Amt = AllocaBuilder.CreateMul(Amt, NumElements); 138 Amt = AllocaBuilder.CreateAdd(Amt, Off); 141 AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt); 707 if (ConstantInt *Amt = dyn_cast<ConstantInt>(I->getOperand(1))) { 710 BitsToClear += Amt [all...] |
H A D | InstCombineSimplifyDemanded.cpp | 890 Constant *Amt = ConstantInt::get(VarX->getType(), ShlAmt - ShrAmt); local 891 New = BinaryOperator::CreateShl(VarX, Amt); 896 Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt); local 897 New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) : 898 BinaryOperator::CreateAShr(VarX, Amt);
|
H A D | InstructionCombining.cpp | 942 int32_t Amt = cast<ConstantInt>(BO->getOperand(1))-> local 944 // Op = LHS << Amt. 946 if (Amt == logScale) { 952 if (Amt < logScale || !Op->hasOneUse()) 958 Op = ConstantInt::get(BO->getType(), Amt - logScale);
|
H A D | InstCombineCompares.cpp | 1407 unsigned Amt = ShAmt->getLimitedValue(TypeBits-1); local 1409 Amt != 0 && RHSV.countTrailingZeros() >= Amt) { 1410 Type *NTy = IntegerType::get(ICI.getContext(), TypeBits - Amt); 1413 ConstantInt::get(RHS->getType(), Amt)),
|
/freebsd-10.0-release/contrib/llvm/tools/clang/lib/Sema/ |
H A D | SemaChecking.cpp | 2384 bool HandleAmount(const analyze_format_string::OptionalAmount &Amt, unsigned k, 2387 const analyze_printf::OptionalAmount &Amt, 2417 const analyze_format_string::OptionalAmount &Amt, 2421 if (Amt.hasDataArgument()) { 2423 unsigned argIndex = Amt.getArgIndex(); 2427 getLocationOfByte(Amt.getStart()), 2446 const analyze_printf::ArgType &AT = Amt.getArgType(S.Context); 2453 getLocationOfByte(Amt.getStart()), 2467 const analyze_printf::OptionalAmount &Amt, 2475 Amt 2416 HandleAmount( const analyze_format_string::OptionalAmount &Amt, unsigned k, const char *startSpecifier, unsigned specifierLen) argument 2465 HandleInvalidAmount( const analyze_printf::PrintfSpecifier &FS, const analyze_printf::OptionalAmount &Amt, unsigned type, const char *startSpecifier, unsigned specifierLen) argument 3060 const OptionalAmount &Amt = FS.getFieldWidth(); local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 681 unsigned Amt = ShiftOp & 0x1f; local 685 << "#" << (Amt == 0 ? 32 : Amt) 688 else if (Amt) { 691 << "#" << Amt
|
/freebsd-10.0-release/contrib/llvm/lib/IR/ |
H A D | ConstantFold.cpp | 252 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); local 253 if (Amt == 0) 255 unsigned ShAmt = Amt->getZExtValue(); 274 ConstantInt *Amt = dyn_cast<ConstantInt>(CE->getOperand(1)); local 275 if (Amt == 0) 277 unsigned ShAmt = Amt->getZExtValue();
|
H A D | Instructions.cpp | 822 static Value *getAISize(LLVMContext &Context, Value *Amt) { argument 823 if (!Amt) 824 Amt = ConstantInt::get(Type::getInt32Ty(Context), 1); 826 assert(!isa<BasicBlock>(Amt) && 828 assert(Amt->getType()->isIntegerTy() && 831 return Amt;
|
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 5039 SDValue Amt = Op.getOperand(2); local 5040 EVT AmtVT = Amt.getValueType(); 5043 DAG.getConstant(BitWidth, AmtVT), Amt); 5044 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 5047 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 5051 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 5068 SDValue Amt = Op.getOperand(2); local 5069 EVT AmtVT = Amt.getValueType(); 5072 DAG.getConstant(BitWidth, AmtVT), Amt); 5073 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 5096 SDValue Amt = Op.getOperand(2); local 5168 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, DebugLoc dl) argument [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 11537 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32); local 11538 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG); 11560 SDValue Amt = Op.getOperand(1); local 11563 if (isSplatVector(Amt.getNode())) { 11564 SDValue SclrAmt = Amt->getOperand(0); 11615 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 11659 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); 11675 Amt.getOpcode() == ISD::BITCAST && 11676 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { 11677 Amt 11726 SDValue Amt = Op.getOperand(1); local 11862 SDValue Amt = Op.getOperand(1); local 16582 SDValue Amt = Mask.getOperand(1); local 16923 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() - local [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 167 unsigned Amt = ARM_AM::getAM2Offset(OffImm); local 169 if (ARM_AM::getSOImmVal(Amt) == -1) 175 .addReg(BaseReg).addImm(Amt) 177 } else if (Amt != 0) { 179 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 193 unsigned Amt = ARM_AM::getAM3Offset(OffImm); local 198 .addReg(BaseReg).addImm(Amt)
|
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 6980 unsigned Amt = Inst.getOperand(2).getImm(); local 6981 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 6983 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 6984 Amt = 0; 6985 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
|