| /broadcom-cfe-1.4.2/cfe/verif/ |
| H A D | vapi.h | 97 .set push ; \
98 .set reorder ; \
103 .set pop
106 .set push ; \
107 .set reorder ; \
111 .set pop
114 .set push ; \
115 .set reorder ; \
119 .set pop
122 .set pus
[all...] |
| H A D | vapi.S | 127 .set noat ; \
139 .set at ; \
144 .set noat ; \
156 .set at
234 .set reorder
367 .set noat
401 .set at
442 .set noat
475 .set at
676 beq t0,zero,3f # skip if no flags set
[all...] |
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/src/ |
| H A D | bcmcore_ircpoll.S | 75 .set push
76 .set noreorder
94 .set pop
100 * Read CP0 registers to determine the set of pending and
111 .set push
112 .set noreorder
113 .set noat
114 .set mips32
140 .set pop
156 .set pus
[all...] |
| H A D | bcmcore_cpuinit.S | 145 .set noreorder
158 mtc0 v0,C0_SR # set up the status register
208 .set reorder
365 .set push
366 .set mips32
398 .set pop
424 .set noreorder
425 .set noat
511 .set reorder
512 .set a
[all...] |
| H A D | bcmcore_l1cache.S | 56 .set push
57 .set mips32
402 .set noreorder
403 .set noat
500 .set pop
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/include/ |
| H A D | cpu_config.h | 80 #define HAZARD .set push ; .set mips64 ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; .set pop
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
| H A D | bcm1480_ircpoll.S | 52 .set mips64
88 .set push
89 .set noreorder
90 .set noat
91 .set mips64
154 /* Current CFE runs with Status.KX set, even when built in
242 .set pop
259 .set push
260 .set noreorder
261 .set mips6
[all...] |
| H A D | sb1_cpuinit.S | 55 .set mips64
79 .set noat
81 .set at
216 .set noreorder
226 mtc0 v0,C0_SR # set up the status register
259 .set noreorder
267 .set reorder
|
| H A D | bcm1480_cpu.S | 61 .set mips64
334 .set noreorder
335 .set noat
412 .set reorder
413 .set at
422 * for us. We are running uncached, with ERL set, so kuseg
|
| H A D | bcm1480_irq.c | 82 extern void bcm1480_update_sr(uint32_t clear, uint32_t set);
100 uint32_t set, clear; local
105 set = 0;
109 set = _MM_MAKEMASK1(S_SR_IMMASK + index);
111 bcm1480_update_sr(clear, set);
416 * free_irq() releases a handler set up by request_irq()
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
| H A D | sb1250_ircpoll.S | 85 .set push
86 .set noreorder
87 .set noat
88 .set mips64
244 .set pop
261 .set push
262 .set noreorder
263 .set mips64
275 or t0,t0,M_SR_IE /* but set IE */
285 .set po
[all...] |
| H A D | sb1_cpuinit.S | 57 .set mips64
80 .set noat
82 .set at
215 .set noreorder
225 mtc0 v0,C0_SR # set up the status register
258 .set noreorder
266 .set reorder
|
| H A D | sb1250_cpu.S | 61 .set mips64
159 * Note: We initially set the coherency attribute
353 .set noreorder
354 .set noat
431 .set reorder
432 .set at
441 * for us. We are running uncached, with ERL set, so kuseg
|
| H A D | sb1250_irq.c | 70 extern void sb1250_update_sr(uint32_t clear, uint32_t set);
88 uint32_t set, clear; local
93 set = 0;
97 set = _MM_MAKEMASK1(S_SR_IMMASK + index);
99 sb1250_update_sr(clear, set);
375 * free_irq() releases a handler set up by request_irq()
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/include/ |
| H A D | cpu_config.h | 80 #define HAZARD .set push ; .set mips64 ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; .set pop
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/include/ |
| H A D | cpu_config.h | 92 .set push ; \
93 .set mips4 ; \
95 .set pop
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/common/src/ |
| H A D | exception.S | 125 .set push ; .set noreorder
142 .set pop
353 .set noreorder
354 .set noat
478 .set at
479 .set reorder
|
| H A D | dev_flash_all.S | 91 * Mask all interrupts. An exception with BEV set would be very bad.
139 bne t0,0xFF,1b # go till bit is set
183 bne t1,0x20,1b # is still set
|
| H A D | zipstart_entry.S | 113 .set noreorder
114 .set noat
227 .set at
228 .set reorder
|
| H A D | zipstart_init.S | 155 .set noreorder
180 .set reorder
186 .set noreorder
194 .set reorder
671 .set push
672 .set mips64
674 .set pop
|
| H A D | init_mips.S | 191 .set noreorder
233 .set reorder
239 .set noreorder
285 .set reorder
325 * Get our GP value from A0 first, then set it back.
377 * The only CP0 init we do is to set K0 to cacheable
526 * If this CPU supports 64-bit registers, set STATUS
692 * high bit set.
699 bge t0,zero,1f # and second entry if high bit set
775 .set pus
[all...] |
| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm95836cpci/src/ |
| H A D | bcm95836cpci_init.S | 105 # is to set w1+w3 < 7. We set w1 = 2 and w3 = 4 below; the w3 value
179 .set mips32
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/src/ |
| H A D | sb1250_memcpy.S | 116 .set noreorder
117 .set noat
118 .set mips64
|
| /broadcom-cfe-1.4.2/cfe/net/ |
| H A D | net_tcp_internal.h | 127 * set of states (defined below)
130 #define TCPSTATE_IN_SET(state,set) ((1 << (state)) & (set))
199 unsigned int tcb_sockflags; /* flags set by user api */
|
| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/src/ |
| H A D | bcm91480ht_init.S | 301 .set push
302 .set mips64
320 .set pop
557 .set push
558 .set noreorder
559 .set nomacro
568 .set pop
|