Searched refs:secondary (Results 1 - 5 of 5) sorted by relevance

/broadcom-cfe-1.4.2/cfe/dev/
H A Ddev_sp1011.c92 int secondary; local
99 secondary = (pci_conf_read(tag, PPB_BUSINFO_REG) >> 8) & 0xFF;
100 pb = pci_businfo(port, secondary);
114 inputs), so we route interrupts only if there are secondary
H A Ddev_ht7520.c117 int secondary; local
138 secondary = (pci_conf_read(br_tag, PPB_BUSINFO_REG) >> 8) & 0xff;
139 pb = pci_businfo(port, secondary);
/broadcom-cfe-1.4.2/cfe/pci/
H A Dldtinit.c87 pci_find_ldt_cap (pcitag_t tag, int secondary) argument
102 if (secondary && type == LDT_COMMAND_TYPE_HOST)
104 if (!secondary && type == LDT_COMMAND_TYPE_SLAVE)
130 ldt_show_cap(pcitag_t tag, int offset, int secondary) argument
136 if (!secondary) {
142 if (!secondary) {
150 ldt_show_cap(pcitag_t tag, int offset, int secondary) argument
644 /* LDT bridge and fabric initialization for a secondary chain */
675 pci_tagprintf(tag, "bridge secondary:\n");
679 pci_tagprintf(tag, "secondary ba
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H A Dpci_internal.h117 unsigned pci_find_ldt_cap (pcitag_t tag, int secondary);
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/
H A Dbcm1480_altcpu.S123 * Initial start addresses for secondary CPUs. Each record below
211 * Start secondary processor(s). These processors will start
213 * for the secondary processor(s) to finish their cache
216 * For simplicity, we serialize starting the secondary processors
260 * Let the secondary CPU(s) out of reset
293 bne v0,zero,1b # Keep going if more secondary CPUs
306 * Finish startup of secondary processor(s) - we pass the relocation
322 * Do this for all secondary CPUs (if any)
334 * Let secondary CPU(s) run their idle loops. Set the
349 bne v0,zero,1b # Keep going if more secondary CPU
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