/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
H A D | bcm1480_hsp_utils.c | 128 #define WRITECSR(x,y) phys_write64(x,y) macro 177 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_0), 182 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_1), 188 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_1), 195 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_2), 200 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_3), 205 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_4), 210 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_RX_HT_RAMALLOC_5), 214 WRITECSR(A_BCM1480_HSP_REGISTER(port, R_BCM1480_HSP_TX_NPC_RAMALLOC), 217 WRITECSR(A_BCM1480_HSP_REGISTE [all...] |
H A D | bcm1480_draminit.c | 285 #define WRITECSR(csr,val) sbwritecsr(csr,val) macro 290 #define WRITECSR(csr,val) *((volatile uint64_t *) (csr)) = (val) macro 1276 WRITECSR(base+R_BCM1480_MC_TIMING1,timing1); 1284 WRITECSR(base+R_BCM1480_MC_TIMING2,timing2); 1323 WRITECSR(base+R_BCM1480_MC_DLL_CFG,mc->dllcfg); 1324 WRITECSR(base+R_BCM1480_MC_DRIVE_CFG,mc->drvcfg); 1331 WRITECSR(base+R_BCM1480_MC_ODT,mc->odtcfg); 1333 WRITECSR(base+R_BCM1480_MC_ODT,mc->odtcfg2); 1344 WRITECSR(PHYS_TO_K1(A_BCM1480_MC_BASE(MC_CHAN1))+R_BCM1480_MC_DRIVE_CFG,drvcfg); 1356 WRITECSR(bas [all...] |
/broadcom-cfe-1.4.2/cfe/arch/ppc/chipset/mpc824x/src/ |
H A D | dev_tulip.c | 372 #define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->membase + (csr), (val))) macro 376 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro 381 WRITECSR((sc), R_CSR_BUSMODE, M_CSR0_SWRESET); \ 693 WRITECSR(sc, R_CSR_TXPOLL, 1); 730 WRITECSR(sc, R_CSR_OPMODE, opmode); 923 WRITECSR(sc, R_CSR_ROM_MII, csr9); 929 WRITECSR(sc, R_CSR_ROM_MII, csr9); 935 WRITECSR(sc, R_CSR_ROM_MII, csr9); 952 WRITECSR(sc, R_CSR_ROM_MII, csr9); 956 WRITECSR(s [all...] |
/broadcom-cfe-1.4.2/cfe/dev/ |
H A D | dev_bcm5700.c | 471 #define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->regbase + (csr), (val))) macro 505 #define WRITECSR(sc,csr,val) (l_phys_write32((sc)->regbase + (csr), (val))) macro 928 WRITECSR(sc, R_EEPROM_ADDR, M_EPADDR_RESET | V_EPADDR_HPERIOD(0x60)); 932 WRITECSR(sc, R_MISC_LOCAL_CTRL, mlctl); 948 WRITECSR(sc, R_EEPROM_ADDR, epaddr); 1026 WRITECSR(sc, R_MDI_CTRL, 0); /* here for now */ 1028 WRITECSR(sc, R_MI_MODE, V_MIMODE_CLKCNT(0x1F)); /* max divider */ 1046 WRITECSR(sc, R_MI_MODE, mode & ~M_MIMODE_POLLING); 1053 WRITECSR(sc, R_MI_COMM, comm); 1065 WRITECSR(s [all...] |
H A D | dev_ns16550.c | 65 #define WRITECSR WRITEREG macro 76 #undef WRITECSR macro 77 #define WRITECSR(sc,r,v) \ macro 171 WRITECSR(softc,R_UART_CFCR,CFCR_DLAB); 172 WRITECSR(softc,R_UART_DATA,brtc & 0xFF); 173 WRITECSR(softc,R_UART_IER,brtc>>8); 174 WRITECSR(softc,R_UART_CFCR,CFCR_8BITS); 179 WRITECSR(softc,R_UART_MCR,MCR_DTR | MCR_RTS | MCR_IENABLE); 181 WRITECSR(softc,R_UART_IER,0); 183 WRITECSR(soft [all...] |
H A D | dev_tulip.c | 311 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro 316 WRITECSR((sc), R_CSR_BUSMODE, M_CSR0_SWRESET); \ 626 WRITECSR(sc, R_CSR_TXPOLL, 1); 661 WRITECSR(sc, R_CSR_OPMODE, opmode); 850 WRITECSR(sc, R_CSR_ROM_MII, csr9); 856 WRITECSR(sc, R_CSR_ROM_MII, csr9); 862 WRITECSR(sc, R_CSR_ROM_MII, csr9); 879 WRITECSR(sc, R_CSR_ROM_MII, csr9); 883 WRITECSR(sc, R_CSR_ROM_MII, csr9 | M_CSR9_SROMCLOCK); 885 WRITECSR(s [all...] |
H A D | dev_ds17887clock.c | 112 #define WRITECSR(p,v) phys_write8((p),(v)) macro 230 WRITECSR(clockbase+DS17887REG_A,DS17887REGA_DV0 | DS17887REGA_DV1 | byte); 235 WRITECSR(clockbase+DS17887REG_B, DS17887REGB_24 | DS17887REGB_DSE | byte ); 309 WRITECSR(clockbase+DS17887REG_B,DS17887REGB_SET | byte); 317 WRITECSR(clockbase+DS17887REG_HR,BCD(hr)); 320 WRITECSR(clockbase+DS17887REG_MN,BCD(min)); 323 WRITECSR(clockbase+DS17887REG_SC,BCD(sec)); 330 WRITECSR(clockbase+DS17887REG_MO,BCD(mo)); 333 WRITECSR(clockbase+DS17887REG_DM,BCD(day)); 336 WRITECSR(clockbas [all...] |
H A D | dev_ds1743.c | 87 #define WRITECSR(p,v) phys_write8((p)^3,(v)) macro 90 #define WRITECSR(p,v) phys_write8((p),(v)) macro 241 WRITECSR(clockbase+DS1743_CONTROL,M_DS1743_R | byte); 252 WRITECSR(clockbase+DS1743_CONTROL,~M_DS1743_R & byte); 289 WRITECSR(clockbase+DS1743_CONTROL,M_DS1743_W | byte); 297 WRITECSR(clockbase+DS1743_HOUR,BCD(hr)); 300 WRITECSR(clockbase+DS1743_MINUTE,BCD(min)); 303 WRITECSR(clockbase+DS1743_SECOND,BCD(sec)); 311 WRITECSR(clockbase+DS1743_MONTH,BCD(mo)); 314 WRITECSR(clockbas [all...] |
H A D | dev_m48txx.c | 95 #define WRITECSR(p,v) phys_write8((p)^0x3,(v)) macro 98 #define WRITECSR(p,v) phys_write8((p),(v)) macro 245 WRITECSR(clockbase+M48TXX_CONTROL,M_M48TXX_R | byte); 267 WRITECSR(clockbase+M48TXX_CONTROL,~M_M48TXX_R & byte); 304 WRITECSR(clockbase+M48TXX_CONTROL,M_M48TXX_W | byte); 312 WRITECSR(clockbase+M48TXX_HOUR,BCD(hr)); 315 WRITECSR(clockbase+M48TXX_MINUTE,BCD(min)); 318 WRITECSR(clockbase+M48TXX_SECOND,BCD(sec)); 325 WRITECSR(clockbase+M48TXX_MONTH,BCD(mo)); 328 WRITECSR(clockbas [all...] |
H A D | dev_bcm4401.c | 287 #define WRITECSR(sc,csr,val) (phys_write32_swapped((sc)->membase + (csr), (val))) macro 291 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro 398 WRITECSR(sc, R_RCV_PTR, V_RPTR_LD(PTR_TO_PCI(nextrxd) & 0xFFF)); 553 WRITECSR(sc, R_XMT_PTR, V_XPTR_LD(PTR_TO_PCI(sc->txdscr_add) & 0xFFF)); 702 WRITECSR(sc, R_MII_STATUS_CONTROL, M_MIICTL_PR | V_MIICTL_MD(0xD)); 706 WRITECSR(sc, R_DEV_CONTROL, devctl); 718 WRITECSR(sc, R_ENET_INT_STATUS, M_EINT_MI); 721 WRITECSR(sc, R_MII_DATA, cmd | V_MIIDATA_SB(K_MII_START)); 743 WRITECSR(sc, R_ENET_INT_STATUS, M_EINT_MI); 747 WRITECSR(s [all...] |
H A D | dev_aic6915.c | 410 #define WRITECSR(sc,csr,val) (phys_write32((sc)->regbase+(csr), (val))) macro 571 WRITECSR(sc, R_RxDescQueue1Ptrs, ptrs); 625 WRITECSR(sc, R_CompletionQueueConsumerIndex, ptrs); 660 WRITECSR(sc, R_TxDescQueueProducerIndex, ptrs); 700 WRITECSR(sc, R_CompletionQueueConsumerIndex, ptrs); 775 WRITECSR(sc, csr, value); 949 WRITECSR(sc, R_BkToBkIPG, ipgt); 950 WRITECSR(sc, R_MacConfig1, config1); 951 WRITECSR(sc, R_MacConfig1, config1 | M_SoftRst); 953 WRITECSR(s [all...] |
H A D | dev_dp83815.c | 270 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro 573 WRITECSR(sc, R_CR, M_CR_TXE | M_CR_RXE); 790 WRITECSR(sc, R_MEAR, ctrl); 796 WRITECSR(sc, R_MEAR, ctrl); 802 WRITECSR(sc, R_MEAR, ctrl); 819 WRITECSR(sc, R_MEAR, ctrl); 823 WRITECSR(sc, R_MEAR, ctrl | M_MEAR_EECLK); 825 WRITECSR(sc, R_MEAR, ctrl); 830 WRITECSR(sc, R_MEAR, ctrl); 842 WRITECSR(s [all...] |
H A D | dev_i82559.c | 307 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro 442 WRITECSR(sc, R_SCB_PTR, arg); 895 WRITECSR(sc, R_MDI_CTL, cmd); 920 WRITECSR(sc, R_MDI_CTL, cmd); 1447 WRITECSR(sc, R_PORT, V_PORT_FUNC(K_PORT_FUNC_SWRESET));
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/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/src/ |
H A D | ui_hspcmds.c | 126 #define WRITECSR(x,y) phys_write64(x,y) macro 296 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) | 300 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) | 304 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) | 332 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) | 336 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) | 340 WRITECSR(ctlreg,V_BCM1480_HSP_TXVIS_RAM_ADDR(idx) | 370 WRITECSR(ctlreg, 379 WRITECSR(ctlreg, 383 WRITECSR(ctlre [all...] |
H A D | ui_pmcmds.c | 85 #define WRITECSR(x,y) phys_write64(x,y) macro 458 WRITECSR(A_BCM1480_PMO_LCL_REGISTER(ring->qno,R_BCM1480_PM_BASE_SIZE), 463 WRITECSR(A_BCM1480_PMO_LCL_REGISTER(ring->qno,R_BCM1480_PM_CONFIG0), 467 WRITECSR(A_BCM1480_PMO_LCL_REGISTER(ring->qno,R_BCM1480_PM_CACHEABILITY), 472 * WRITECSR(A_BCM1480_PMO_LCL_REGISTER(ring->qno,R_BCM1480_PM_INT_WMK), 483 * WRITECSR(A_BCM1480_PMO_LCL_REGISTER(ring->qno,R_BCM1480_PM_INT_CNFG), int_cnfg_val); 487 WRITECSR(A_BCM1480_PMO_LCL_REGISTER(ring->qno,R_BCM1480_PM_DESC_MERGE_TIMER), 16); 495 WRITECSR(A_BCM1480_PMI_LCL_REGISTER(ring->qno,R_BCM1480_PM_BASE_SIZE), 500 WRITECSR(A_BCM1480_PMI_LCL_REGISTER(ring->qno,R_BCM1480_PM_CONFIG0), 504 WRITECSR(A_BCM1480_PMI_LCL_REGISTE [all...] |
H A D | ui_swtrace.c | 78 //#define WRITECSR(x,y) printf("WRITE_REG %016llx %016llx\n",(uint64_t)(x),(uint64_t)(y));phys_write64(x,y) 79 #define WRITECSR(x,y) phys_write64(x,y) macro
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H A D | cfe_dmtest.c | 1424 #define WRITECSR(csr,val) *((volatile uint64_t *) (csr)) = (val) macro 1427 WRITECSR(PHYS_TO_K1(A_GPIO_PIN_SET), M_GPIO_DEBUG_LED); 1429 WRITECSR(PHYS_TO_K1(A_GPIO_PIN_CLR), M_GPIO_DEBUG_LED); 1433 #undef WRITECSR macro
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/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
H A D | sb1250_draminit.c | 263 #define WRITECSR(csr,val) sbwritecsr(csr,val) macro 269 #define WRITECSR(csr,val) *((volatile uint64_t *) (csr)) = (val) macro 1184 WRITECSR(base+R_MC_TIMING1,timing1); 1193 WRITECSR(base+R_MC_MCLK_CFG,mclkcfg); 1277 WRITECSR(base+R_MC_TIMING1,timing1); 1286 WRITECSR(base+R_MC_MCLK_CFG,mclkcfg); 1443 WRITECSR(base+R_SMB_FREQ,K_SMB_FREQ_100KHZ); 1444 WRITECSR(base+R_SMB_CONTROL,0); 1483 WRITECSR(base+R_SMB_STATUS,status); 1525 WRITECSR(bas [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/ |
H A D | sb_pci_machdep.c | 105 #define WRITECSR(x,v) \ macro 265 WRITECSR(R_PCI_CONTROL, ctrl); 268 WRITECSR(R_PCI_CONTROL, ctrl); 271 WRITECSR(R_PCI_CONTROL, ctrl); 279 WRITECSR(R_PCI_ARB_CONTROL, M_PCIARB_EA); 284 WRITECSR(R_PCI_ARB_CONTROL, M_PCIARB_IA); 288 WRITECSR(R_SB_TO_PCI_TRANSLATION0, 303 WRITECSR(R_INT_MASK, M_PCIINT_PA | M_PCIINT_PB); 438 WRITECSR(R_SB_TO_PCI_TRANSLATION1, 450 WRITECSR(R_SB_TO_PCI_TRANSLATION [all...] |
H A D | dev_sb_mac.c | 352 #define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) macro 459 WRITECSR(sc, R_RCV_PTR, V_RPTR_LD(PTR_TO_PCI(sc, nextrxd) & 0xFFF)); 609 WRITECSR(sc, R_XMT_PTR, 777 WRITECSR(sc, R_MII_STATUS_CONTROL, M_MIICTL_PR | V_MIICTL_MD(0xD)); 781 WRITECSR(sc, R_DEV_CONTROL, devctl); 786 WRITECSR(sc, R_MII_STATUS_CONTROL, M_MIICTL_PR | V_MIICTL_MD(0x9)); 789 WRITECSR(sc, R_ENET_CONTROL, enetctl); 800 WRITECSR(sc, R_ENET_INT_STATUS, M_EINT_MI); 805 WRITECSR(sc, R_MII_DATA, cmd | V_MIIDATA_SB(K_MII_START)); 827 WRITECSR(s [all...] |
H A D | sb_utils.c | 207 #define WRITECSR(x,v) \ macro 218 WRITECSR(R_WATCHDOGCNTR, 1); 328 WRITECSR(R_CLOCKCONTROLN, new_n); 329 WRITECSR(R_CLOCKCONTROLSB, new_sb); 330 WRITECSR(R_CLOCKCONTROLPCI, new_pci); 332 WRITECSR(R_CLOCKCONTROLMII, sb_clock_table[i].m25); 347 #define WRITECSR(x,v) \ macro 354 WRITECSR(R_WATCHDOGCNTR, 1); 587 WRITECSR(R_CLOCKCONTROLN, new_n); 588 WRITECSR(R_CLOCKCONTROLM [all...] |