1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * NS DP83815 Ethernet Driver File: dev_dp83815.c 5 * 6 * Author: Ed Satterthwaite 7 * 8 ********************************************************************* 9 * 10 * Copyright 2000,2001,2002,2003 11 * Broadcom Corporation. All rights reserved. 12 * 13 * This software is furnished under license and may be used and 14 * copied only in accordance with the following terms and 15 * conditions. Subject to these conditions, you may download, 16 * copy, install, use, modify and distribute modified or unmodified 17 * copies of this software in source and/or binary form. No title 18 * or ownership is transferred hereby. 19 * 20 * 1) Any source code used, modified or distributed must reproduce 21 * and retain this copyright notice and list of conditions 22 * as they appear in the source file. 23 * 24 * 2) No right is granted to use any trade name, trademark, or 25 * logo of Broadcom Corporation. The "Broadcom Corporation" 26 * name may not be used to endorse or promote products derived 27 * from this software without the prior written permission of 28 * Broadcom Corporation. 29 * 30 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 32 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 33 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 34 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 35 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 38 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 39 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 40 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 41 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 42 * THE POSSIBILITY OF SUCH DAMAGE. 43 ********************************************************************* */ 44 45#include "cfe.h" 46#include "lib_physio.h" 47 48#ifdef CPUCFG_MEMCPY 49#error "this is broken now." 50extern void *CPUCFG_MEMCPY(void *dest, const void *src, size_t cnt); 51#define blockcopy CPUCFG_MEMCPY 52#else 53#define blockcopy memcpy 54#endif 55#include "cfe_irq.h" 56 57#include "net_enet.h" 58 59#include "pcivar.h" 60#include "pcireg.h" 61 62#include "dp83815.h" 63#include "mii.h" 64 65/* This is a driver for the National Semiconductor DP83815 (MacPhyter) 66 10/100 MAC with integrated PHY. 67 68 The current version has been developed for the Netgear FA311 and 69 FA312 NICs. These include an EEPROM with automatically loaded 70 setup information that includes station address filtering. 71 Operation without such an EEPROM has not been tested. 72 73 The SB1250 version takes advantage of DMA coherence and uses 74 "preserve bit lanes" addresses for all accesses that cross the 75 ZBbus-PCI bridge. For non-coherent memory systems, all addresses 76 of descriptors are converted to do uncached access, and packet data 77 is flushed as required. */ 78 79#ifndef MACPHYTER_DEBUG 80#define MACPHYTER_DEBUG 0 81#endif 82#ifndef MACPHYTER_TEST 83#define MACPHYTER_TEST 0 84#endif 85 86#if ((ENDIAN_BIG + ENDIAN_LITTLE) != 1) 87#error "dev_dp83815: system endian not set" 88#endif 89 90/* Set IPOLL to drive processing through the pseudo-interrupt 91 dispatcher. Set XPOLL to drive processing by an external polling 92 agent. Setting both is ok. */ 93 94#ifndef IPOLL 95#define IPOLL 0 96#endif 97#ifndef XPOLL 98#define XPOLL 1 99#endif 100 101#define MIN_ETHER_PACK (ENET_MIN_PKT+ENET_CRC_SIZE) /* min packet size */ 102#define MAX_ETHER_PACK (ENET_MAX_PKT+ENET_CRC_SIZE) /* max packet size */ 103 104/* Packet buffers. For the DP83815, an rx packet must be aligned to a 105 32-bit word boundary, and we would like it aligned to a cache line 106 boundary for performance. Also, the buffers "should" be allocated 107 in 32 byte multiples (5.3.2). */ 108 109#define ETH_PKTBUF_LEN (((MAX_ETHER_PACK+31)/32)*32) 110 111typedef struct eth_pkt_s { 112 queue_t next; /* 8 */ 113 uint8_t *buffer; /* 4 */ 114 uint32_t flags; /* 4 */ 115 int32_t length; /* 4 */ 116 uint32_t unused[3]; /* 12 */ 117 uint8_t data[ETH_PKTBUF_LEN]; 118} eth_pkt_t; 119 120#define CACHE_ALIGN 32 121#define ALIGN(n,align) (((n)+((align)-1)) & ~((align)-1)) 122 123#define ETH_PKTBUF_LINES ((sizeof(eth_pkt_t) + (CACHE_ALIGN-1))/CACHE_ALIGN) 124#define ETH_PKTBUF_SIZE (ETH_PKTBUF_LINES*CACHE_ALIGN) 125#define ETH_PKTBUF_OFFSET (offsetof(eth_pkt_t, data)) 126 127#define ETH_PKT_BASE(data) ((eth_pkt_t *)((data) - ETH_PKTBUF_OFFSET)) 128 129/* packet flags */ 130#define ETH_TX_SETUP 1 /* assumes Perfect Filtering format */ 131 132static void 133show_packet(char c, eth_pkt_t *pkt) 134{ 135 int i; 136 int n = (pkt->length < 32 ? pkt->length : 32); 137 138 xprintf("%c[%4d]:", c, pkt->length); 139 for (i = 0; i < n; i++) { 140 if (i % 4 == 0) 141 xprintf(" "); 142 xprintf("%02x", pkt->buffer[i]); 143 } 144 xprintf("\n"); 145} 146 147 148/* Descriptor structures. NOTE: To avoid having descriptors straddle 149 cache lines, we append a pad word, ignored by DMA, to each. */ 150 151typedef struct rx_dscr { 152 pci_addr_t rxd_link; 153 uint32_t rxd_cmdsts; 154 pci_addr_t rxd_bufptr; 155 uint32_t rxd_pad; 156} rx_dscr; 157 158typedef struct tx_dscr { 159 pci_addr_t txd_link; 160 uint32_t txd_cmdsts; 161 pci_addr_t txd_bufptr; 162 uint32_t txd_pad; 163} tx_dscr; 164 165 166/* Driver data structures */ 167 168typedef enum { 169 eth_state_uninit, 170 eth_state_off, 171 eth_state_on, 172 eth_state_broken 173} eth_state_t; 174 175#define ETH_PKTPOOL_SIZE 32 176 177typedef struct dp83815_softc { 178 uint32_t membase; 179 uint8_t irq; /* interrupt mapping (used if IPOLL) */ 180 pcitag_t tag; /* tag for configuration registers */ 181 182 uint8_t hwaddr[ENET_ADDR_LEN]; 183 uint16_t device; /* chip device code */ 184 uint8_t revision; /* chip revision and step */ 185 186 eth_state_t state; /* current state */ 187 uint32_t intmask; /* interrupt mask */ 188 189 /* These fields are set before calling dp83815_hwinit */ 190 int linkspeed; /* encodings from cfe_ioctl */ 191 int loopback; 192 193 /* Packet free list */ 194 queue_t freelist; 195 uint8_t *pktpool; 196 queue_t rxqueue; 197 198 /* The descriptor tables */ 199 uint8_t *rxdscrmem; /* receive descriptors */ 200 uint8_t *txdscrmem; /* transmit descriptors */ 201 202 /* These fields keep track of where we are in tx/rx processing */ 203 volatile rx_dscr *rxdscr_start; /* beginning of ring */ 204 volatile rx_dscr *rxdscr_end; /* end of ring */ 205 volatile rx_dscr *rxdscr_remove; /* next one we expect DMA to use */ 206 volatile rx_dscr *rxdscr_add; /* next place to put a buffer */ 207 int rxdscr_onring; 208 209 volatile tx_dscr *txdscr_start; /* beginning of ring */ 210 volatile tx_dscr *txdscr_end; /* end of ring */ 211 volatile tx_dscr *txdscr_remove; /* next one we will use for tx */ 212 volatile tx_dscr *txdscr_add; /* next place to put a buffer */ 213 214 cfe_devctx_t *devctx; 215 216 /* These fields describe the PHY */ 217 int phy_addr; 218 int phy_check; 219 uint32_t phy_status; 220 uint32_t phy_vendor; 221 uint16_t phy_device; 222 223 /* Statistics */ 224 uint32_t inpkts; 225 uint32_t outpkts; 226 uint32_t interrupts; 227 uint32_t rx_interrupts; 228 uint32_t tx_interrupts; 229 uint32_t bus_errors; 230} dp83815_softc; 231 232 233/* Entry to and exit from critical sections (currently relative to 234 interrupts only, not SMP) */ 235 236#if CFG_INTERRUPTS 237#define CS_ENTER(sc) cfe_disable_irq(sc->irq) 238#define CS_EXIT(sc) cfe_enable_irq(sc->irq) 239#else 240#define CS_ENTER(sc) ((void)0) 241#define CS_EXIT(sc) ((void)0) 242#endif 243 244 245/* Driver parameterization */ 246 247#define MAXRXDSCR 32 248#define MAXTXDSCR 32 249#define MINRXRING 8 250 251 252/* Prototypes */ 253 254static void dp83815_ether_probe(cfe_driver_t *drv, 255 unsigned long probe_a, unsigned long probe_b, 256 void *probe_ptr); 257 258 259/* Address mapping macros */ 260 261/* Note that PTR_TO_PHYS only works with 32-bit addresses, but then 262 so does the dp83815. */ 263#define PTR_TO_PHYS(x) (PHYSADDR((uintptr_t)(x))) 264#define PHYS_TO_PTR(a) ((uint8_t *)KERNADDR(a)) 265 266#define PCI_TO_PTR(a) (PHYS_TO_PTR(PCI_TO_PHYS(a))) 267#define PTR_TO_PCI(x) (PHYS_TO_PCI(PTR_TO_PHYS(x))) 268 269#define READCSR(sc,csr) (phys_read32((sc)->membase + (csr))) 270#define WRITECSR(sc,csr,val) (phys_write32((sc)->membase + (csr), (val))) 271 272 273#define RESET_ADAPTER(sc) \ 274 { \ 275 /* XXX */ \ 276 } 277 278 279/* Debugging */ 280 281static void 282dumpstat(dp83815_softc *sc) 283{ 284 xprintf("-- CR = %08X CFG = %08x\n", 285 READCSR(sc, R_CR), READCSR(sc, R_CFG)); 286} 287 288static void 289dumpcsrs(dp83815_softc *sc) 290{ 291 int reg; 292 293 xprintf("-------------\n"); 294 for (reg = 0; reg < R_MIBC; reg += 4) { 295 xprintf("CSR %02X = %08X\n", reg, READCSR(sc, reg)); 296 } 297 xprintf("-------------\n"); 298} 299 300 301/* Packet management */ 302 303/* ********************************************************************* 304 * ETH_ALLOC_PKT(sc) 305 * 306 * Allocate a packet from the free list. 307 * 308 * Input parameters: 309 * sc - eth structure 310 * 311 * Return value: 312 * pointer to packet structure, or NULL if none available 313 ********************************************************************* */ 314static eth_pkt_t * 315eth_alloc_pkt(dp83815_softc *sc) 316{ 317 eth_pkt_t *pkt; 318 319 CS_ENTER(sc); 320 pkt = (eth_pkt_t *) q_deqnext(&sc->freelist); 321 CS_EXIT(sc); 322 if (!pkt) return NULL; 323 324 pkt->buffer = pkt->data; 325 pkt->length = ETH_PKTBUF_LEN; 326 pkt->flags = 0; 327 328 return pkt; 329} 330 331 332/* ********************************************************************* 333 * ETH_FREE_PKT(sc,pkt) 334 * 335 * Return a packet to the free list 336 * 337 * Input parameters: 338 * sc - sbmac structure 339 * pkt - packet to return 340 * 341 * Return value: 342 * nothing 343 ********************************************************************* */ 344static void 345eth_free_pkt(dp83815_softc *sc, eth_pkt_t *pkt) 346{ 347 CS_ENTER(sc); 348 q_enqueue(&sc->freelist, &pkt->next); 349 CS_EXIT(sc); 350} 351 352 353/* ********************************************************************* 354 * ETH_INITFREELIST(sc) 355 * 356 * Initialize the buffer free list for this mac. The memory 357 * allocated to the free list is carved up and placed on a linked 358 * list of buffers for use by the mac. 359 * 360 * Input parameters: 361 * sc - eth structure 362 * 363 * Return value: 364 * nothing 365 ********************************************************************* */ 366static void 367eth_initfreelist(dp83815_softc *sc) 368{ 369 int idx; 370 uint8_t *ptr; 371 eth_pkt_t *pkt; 372 373 q_init(&sc->freelist); 374 375 ptr = sc->pktpool; 376 for (idx = 0; idx < ETH_PKTPOOL_SIZE; idx++) { 377 pkt = (eth_pkt_t *) ptr; 378 eth_free_pkt(sc, pkt); 379 ptr += ETH_PKTBUF_SIZE; 380 } 381} 382 383 384/* Utilities */ 385 386static const char * 387dp83815_devname(dp83815_softc *sc) 388{ 389 return (sc->devctx != NULL ? cfe_device_name(sc->devctx) : "eth?"); 390} 391 392 393/* Descriptor ring management */ 394 395static int 396dp83815_add_rcvbuf(dp83815_softc *sc, eth_pkt_t *pkt) 397{ 398 volatile rx_dscr *rxd; 399 volatile rx_dscr *nextrxd; 400 401 rxd = sc->rxdscr_add; 402 403 /* Figure out where the next descriptor will go */ 404 nextrxd = rxd+1; 405 if (nextrxd == sc->rxdscr_end) { 406 nextrxd = sc->rxdscr_start; 407 } 408 409 /* If the next one is the same as our remove pointer, the ring is 410 considered full. */ 411 if (nextrxd == sc->rxdscr_remove) return -1; 412 413 rxd->rxd_bufptr = PTR_TO_PCI(pkt->buffer); 414 rxd->rxd_cmdsts = M_DES1_INTR | V_DES1_SIZE(ETH_PKTBUF_LEN); 415 416 /* success, advance the pointer */ 417 sc->rxdscr_add = nextrxd; 418 419 return 0; 420} 421 422static void 423dp83815_fillrxring(dp83815_softc *sc) 424{ 425 eth_pkt_t *pkt; 426 427 CS_ENTER(sc); 428 while (1) { 429 if (sc->rxdscr_onring >= MINRXRING) { 430 CS_EXIT(sc); 431 break; 432 } 433 CS_EXIT(sc); 434 pkt = eth_alloc_pkt(sc); 435 if (pkt == NULL) { 436 /* could not allocate a buffer */ 437 break; 438 } 439 if (dp83815_add_rcvbuf(sc, pkt) != 0) { 440 /* could not add buffer to ring */ 441 eth_free_pkt(sc, pkt); 442 break; 443 } 444 CS_ENTER(sc); 445 sc->rxdscr_onring++; 446 } 447} 448 449 450/* ********************************************************************* 451 * DP83815_RX_CALLBACK(sc, pkt) 452 * 453 * Receive callback routine. This routine is invoked when a 454 * buffer queued for receives is filled. In this simple driver, 455 * all we do is add the packet to a per-MAC queue for later 456 * processing, and try to put a new packet in the place of the one 457 * that was removed from the queue. 458 * 459 * Input parameters: 460 * sc - interface 461 * ptk - packet context (eth_pkt structure) 462 * 463 * Return value: 464 * nothing 465 ********************************************************************* */ 466static void 467dp83815_rx_callback(dp83815_softc *sc, eth_pkt_t *pkt) 468{ 469 if (MACPHYTER_DEBUG) show_packet('>', pkt); /* debug */ 470 471 CS_ENTER(sc); 472 q_enqueue(&sc->rxqueue, &pkt->next); 473 CS_EXIT(sc); 474 sc->inpkts++; 475} 476 477 478static void 479dp83815_procrxring(dp83815_softc *sc) 480{ 481 volatile rx_dscr *rxd; 482 eth_pkt_t *pkt; 483 eth_pkt_t *newpkt; 484 uint32_t cmdsts; 485 486 for (;;) { 487 rxd = sc->rxdscr_remove; 488 489 cmdsts = rxd->rxd_cmdsts; 490 if ((cmdsts & M_DES1_OWN) == 0) { 491 /* end of ring, no more packets */ 492 break; 493 } 494 495 pkt = ETH_PKT_BASE(PCI_TO_PTR(rxd->rxd_bufptr)); 496 pkt->length = G_DES1_SIZE(cmdsts) - ENET_CRC_SIZE; 497 498 /* Drop error packets */ 499 if (cmdsts & M_DES1_RX_ERRORS) { 500#if MACPHYTER_DEBUG 501 if (pkt->length >= MIN_ETHER_PACK - ENET_CRC_SIZE) 502 xprintf("%s: rx error %08X\n", dp83815_devname(sc), cmdsts); 503#endif 504 newpkt = pkt; /* recycle the buffer */ 505 } 506 else { 507 /* Pass up the packet */ 508 dp83815_rx_callback(sc, pkt); 509 510 /* put a buffer back on the ring to replace this one */ 511 newpkt = eth_alloc_pkt(sc); 512 } 513 514 /* update the pointer, accounting for buffer wrap. */ 515 rxd++; 516 if (rxd == sc->rxdscr_end) 517 rxd = sc->rxdscr_start; 518 sc->rxdscr_remove = rxd; 519 520 if (newpkt) { 521 /* The ring must have space now. */ 522 dp83815_add_rcvbuf(sc, newpkt); 523 } 524 else { 525 CS_ENTER(sc); 526 sc->rxdscr_onring--; 527 CS_EXIT(sc); 528 } 529 } 530} 531 532 533static int 534dp83815_add_txbuf(dp83815_softc *sc, eth_pkt_t *pkt) 535{ 536 volatile tx_dscr *txd; 537 volatile tx_dscr *nexttxd; 538 539 txd = sc->txdscr_add; 540 541 /* Figure out where the next descriptor will go */ 542 nexttxd = (txd+1); 543 if (nexttxd == sc->txdscr_end) { 544 nexttxd = sc->txdscr_start; 545 } 546 547 /* If the next one is the same as our remove pointer, 548 the ring is considered full. (it actually has room for 549 one more, but we reserve the remove == add case for "empty") */ 550 551 if (nexttxd == sc->txdscr_remove) return -1; 552 553 txd->txd_bufptr = PTR_TO_PCI(pkt->buffer); 554 txd->txd_cmdsts = M_DES1_INTR | M_DES1_OWN | V_DES1_SIZE(pkt->length); 555 556 /* success, advance the pointer */ 557 sc->txdscr_add = nexttxd; 558 559 return 0; 560} 561 562 563static int 564dp83815_transmit(dp83815_softc *sc,eth_pkt_t *pkt) 565{ 566 int rv; 567 568 if (MACPHYTER_DEBUG) show_packet('<', pkt); /* debug */ 569 570 rv = dp83815_add_txbuf(sc, pkt); 571 sc->outpkts++; 572 573 WRITECSR(sc, R_CR, M_CR_TXE | M_CR_RXE); 574 return rv; 575} 576 577 578static void 579dp83815_proctxring(dp83815_softc *sc) 580{ 581 volatile tx_dscr *txd; 582 eth_pkt_t *pkt; 583 uint32_t cmdsts; 584 585 for (;;) { 586 txd = sc->txdscr_remove; 587 588 if (txd == sc->txdscr_add) { 589 /* ring is empty, no buffers to process */ 590 break; 591 } 592 593 cmdsts = txd->txd_cmdsts; 594 if (cmdsts & M_DES1_OWN) { 595 /* Reached a packet still being transmitted */ 596 break; 597 } 598 599 /* Just free the packet */ 600 pkt = ETH_PKT_BASE(PCI_TO_PTR(txd->txd_bufptr)); 601 eth_free_pkt(sc, pkt); 602 603 /* update the pointer, accounting for buffer wrap. */ 604 txd++; 605 if (txd == sc->txdscr_end) 606 txd = sc->txdscr_start; 607 608 sc->txdscr_remove = txd; 609 } 610} 611 612 613static void 614dp83815_initrings(dp83815_softc *sc) 615{ 616 volatile tx_dscr *txd, *txn; 617 volatile rx_dscr *rxd, *rxn; 618 619 /* Claim ownership of all descriptors for the driver */ 620 621 for (txd = sc->txdscr_start; txd != sc->txdscr_end; txd++) { 622 txn = txd + 1; 623 if (txn == sc->txdscr_end) txn = sc->txdscr_start; 624 txd->txd_link = PTR_TO_PCI(txn); 625 txd->txd_cmdsts = 0; 626 txd->txd_pad = 0; 627 } 628 for (rxd = sc->rxdscr_start; rxd != sc->rxdscr_end; rxd++) { 629 rxn = rxd + 1; 630 if (rxn == sc->rxdscr_end) rxn = sc->rxdscr_start; 631 rxd->rxd_link = PTR_TO_PCI(rxn); 632 rxd->rxd_cmdsts = M_DES1_OWN; 633 rxd->rxd_pad = 0; 634 } 635 636 /* Init the ring pointers */ 637 638 sc->txdscr_add = sc->txdscr_remove = sc->txdscr_start; 639 sc->rxdscr_add = sc->rxdscr_remove = sc->rxdscr_start; 640 sc->rxdscr_onring = 0; 641 642 /* Add stuff to the receive ring */ 643 644 dp83815_fillrxring(sc); 645} 646 647 648/* Allocate an integral number of cache lines suitable for DMA access. */ 649static uint8_t * 650dma_alloc(size_t size, unsigned int align) 651{ 652 uint8_t *base; 653 size_t len = ALIGN(size, CACHE_ALIGN); 654 655 base = KMALLOC(len, ALIGN(align, CACHE_ALIGN)); 656 if (base != NULL) 657 CACHE_DMA_INVAL(base, len); 658 return base; 659} 660 661static int 662dp83815_init(dp83815_softc *sc) 663{ 664 /* Allocate descriptor rings */ 665 sc->rxdscrmem = CACHE_DMA_SHARED(dma_alloc(MAXRXDSCR*sizeof(rx_dscr), CACHE_ALIGN)); 666 sc->txdscrmem = CACHE_DMA_SHARED(dma_alloc(MAXTXDSCR*sizeof(tx_dscr), CACHE_ALIGN)); 667 668 /* Allocate buffer pool */ 669 sc->pktpool = dma_alloc(ETH_PKTPOOL_SIZE*ETH_PKTBUF_SIZE, CACHE_ALIGN); 670 eth_initfreelist(sc); 671 q_init(&sc->rxqueue); 672 673 /* Fill in pointers to the rings */ 674 sc->rxdscr_start = (volatile rx_dscr *) (sc->rxdscrmem); 675 sc->rxdscr_end = sc->rxdscr_start + MAXRXDSCR; 676 sc->rxdscr_add = sc->rxdscr_start; 677 sc->rxdscr_remove = sc->rxdscr_start; 678 sc->rxdscr_onring = 0; 679 680 sc->txdscr_start = (volatile tx_dscr *) (sc->txdscrmem); 681 sc->txdscr_end = sc->txdscr_start + MAXTXDSCR; 682 sc->txdscr_add = sc->txdscr_start; 683 sc->txdscr_remove = sc->txdscr_start; 684 685 dp83815_initrings(sc); 686 687 return 0; 688} 689 690 691static void 692dp83815_resetrings(dp83815_softc *sc) 693{ 694 volatile tx_dscr *txd; 695 volatile rx_dscr *rxd; 696 eth_pkt_t *pkt; 697 698 /* Free already-sent descriptors and buffers */ 699 dp83815_proctxring(sc); 700 701 /* Free any pending but unsent */ 702 txd = sc->txdscr_remove; 703 while (txd != sc->txdscr_add) { 704 txd->txd_cmdsts &=~ M_DES1_OWN; 705 pkt = ETH_PKT_BASE(PCI_TO_PTR(txd->txd_bufptr)); 706 eth_free_pkt(sc, pkt); 707 708 txd++; 709 if (txd == sc->txdscr_end) 710 txd = sc->txdscr_start; 711 } 712 sc->txdscr_add = sc->txdscr_remove; 713 714 /* Discard any received packets as well as all free buffers */ 715 rxd = sc->rxdscr_remove; 716 while (rxd != sc->rxdscr_add) { 717 rxd->rxd_cmdsts |= M_DES1_OWN; 718 pkt = ETH_PKT_BASE(PCI_TO_PTR(rxd->rxd_bufptr)); 719 eth_free_pkt(sc, pkt); 720 721 rxd++; 722 if (rxd == sc->rxdscr_end) 723 rxd = sc->rxdscr_start; 724 CS_ENTER(sc); 725 sc->rxdscr_onring--; 726 CS_EXIT(sc); 727 } 728 729 /* Reestablish the initial state. */ 730 dp83815_initrings(sc); 731} 732 733 734#if 0 /* XXX Multicast filtering not yet implemented. */ 735/* CRCs */ 736 737static uint32_t 738dp83815_crc32(const uint8_t *databuf, unsigned int datalen) 739{ 740 unsigned int idx, bit, data; 741 uint32_t crc; 742 743 crc = 0xFFFFFFFFUL; 744 for (idx = 0; idx < datalen; idx++) 745 for (data = *databuf++, bit = 0; bit < 8; bit++, data >>= 1) 746 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? ENET_CRC32_POLY : 0); 747 return crc; 748} 749 750#define dp83815_mchash(mca) (dp83815_crc32((mca), 6) & 0x1FF) 751#endif 752 753 754#if MACPHYTER_TEST 755/* EEPROM access */ 756 757/* Current NICs use the EEPROM auto-load feature and there is no need 758 for explicit EEPROM access. The following routines are included 759 for future applications and have been tested (Netgear FA311). */ 760 761/* 762 * The recommended EEPROM is the NM9306. 763 * Delays below are chosen to meet specs for NS93C64 (slow M variant). 764 * Current parts are faster. 765 * Reference: NS Memory Data Book, 1994 766 */ 767 768#define EEPROM_SIZE (2*0x0C) 769#define EEPROM_MAX_CYCLES 32 770 771#define EEPROM_CMD_BITS 3 772#define EEPROM_ADDR_BITS 6 773 774#define K_EEPROM_READ_CMD 06 775#define K_EEPROM_WRITE_CMD 05 776 777#define EEPROM_CRC_INDEX (EEPROM_SIZE-2) 778 779#define EEPROM_WORD(rom,offset) ((rom)[offset] | ((rom)[offset+1] << 8)) 780 781static void 782eeprom_idle_state(dp83815_softc *sc) 783{ 784 uint32_t ctrl; 785 unsigned int i; 786 787 ctrl = READCSR(sc, R_MEAR); 788 789 ctrl |= M_MEAR_EESEL; 790 WRITECSR(sc, R_MEAR, ctrl); 791 cfe_nsleep(100); /* CS setup (Tcss=100) */ 792 793 /* Run the clock through the maximum number of pending read cycles */ 794 for (i = 0; i < EEPROM_MAX_CYCLES*2; i++) { 795 ctrl ^= M_MEAR_EECLK; 796 WRITECSR(sc, R_MEAR, ctrl); 797 cfe_nsleep(1000); /* SK period (Fsk=0.5MHz) */ 798 } 799 800 /* Deassert EEPROM Chip Select */ 801 ctrl &=~ M_MEAR_EESEL; 802 WRITECSR(sc, R_MEAR, ctrl); 803 cfe_nsleep(50); /* CS recovery (Tsks=50) */ 804} 805 806static void 807eeprom_send_command_bit(dp83815_softc *sc, unsigned int data) 808{ 809 uint32_t ctrl; 810 811 ctrl = READCSR(sc, R_MEAR); 812 813 /* Place the data bit on the bus */ 814 if (data == 1) 815 ctrl |= M_MEAR_EEDI; 816 else 817 ctrl &=~ M_MEAR_EEDI; 818 819 WRITECSR(sc, R_MEAR, ctrl); 820 cfe_nsleep(360); /* setup: Tdis=200 */ 821 822 /* Now clock the data into the EEPROM */ 823 WRITECSR(sc, R_MEAR, ctrl | M_MEAR_EECLK); 824 cfe_nsleep(900); /* clock high, Tskh=500 */ 825 WRITECSR(sc, R_MEAR, ctrl); 826 cfe_nsleep(450); /* clock low, Tskl=250 */ 827 828 /* Now clear the data bit */ 829 ctrl &=~ M_MEAR_EEDI; /* data invalid, Tidh=20 for SK^ */ 830 WRITECSR(sc, R_MEAR, ctrl); 831 cfe_nsleep(270); /* min cycle, 1/Fsk=2000 */ 832} 833 834static uint16_t 835eeprom_read_bit(dp83815_softc *sc) 836{ 837 uint32_t ctrl; 838 839 ctrl = READCSR(sc, R_MEAR); 840 841 /* Generate a clock cycle before doing a read */ 842 WRITECSR(sc, R_MEAR, ctrl | M_MEAR_EECLK); /* rising edge */ 843 cfe_nsleep(1000); /* clock high, Tskh=500, Tpd=1000 */ 844 WRITECSR(sc, R_MEAR, ctrl); /* falling edge */ 845 cfe_nsleep(1000); /* clock low, 1/Fsk=2000 */ 846 847 ctrl = READCSR(sc, R_MEAR); 848 return ((ctrl & M_MEAR_EEDO) != 0 ? 1 : 0); 849} 850 851#define CMD_BIT_MASK (1 << (EEPROM_CMD_BITS+EEPROM_ADDR_BITS-1)) 852 853static uint16_t 854eeprom_read_word(dp83815_softc *sc, unsigned int index) 855{ 856 uint16_t command, word; 857 uint32_t ctrl; 858 unsigned int i; 859 860 ctrl = READCSR(sc, R_MEAR) | M_MEAR_EESEL; 861 862 /* Assert the EEPROM CS line */ 863 WRITECSR(sc, R_MEAR, ctrl); 864 cfe_nsleep(100); /* CS setup, Tcss = 100 */ 865 866 /* Send the read command to the EEPROM */ 867 command = (K_EEPROM_READ_CMD << EEPROM_ADDR_BITS) | index; 868 for (i = 0; i < EEPROM_CMD_BITS+EEPROM_ADDR_BITS; i++) { 869 eeprom_send_command_bit(sc, (command & CMD_BIT_MASK) != 0 ? 1 : 0); 870 command <<= 1; 871 } 872 873 /* Now read the bits from the EEPROM (MSB first) */ 874 word = 0; 875 for (i = 0; i < 16; ++i) { 876 word <<= 1; 877 word |= eeprom_read_bit(sc); 878 } 879 880 /* Clear the EEPROM CS Line, CS hold, Tcsh = 0 */ 881 WRITECSR(sc, R_MEAR, ctrl &~ M_MEAR_EESEL); 882 883 return word; 884} 885 886 887/**************************************************************************** 888 * eeprom_checksum() 889 * 890 * Calculate the checksum of the EEPROM and return it. See Section 891 * 4.2.4 for the algorithm. 892 ***************************************************************************/ 893 894static uint16_t 895eeprom_checksum(const uint8_t rom[]) 896{ 897 uint16_t sum; 898 int i; 899 900 sum = 0; 901 for (i = 0; i < EEPROM_SIZE-1; i++) 902 sum += rom[i]; 903 sum ^= 0xFF; 904 return (((sum + 1) & 0xFF) << 8) | 0x55; 905} 906 907 908/**************************************************************************** 909 * eeprom_read_all(sc, uint8_t dest) 910 * 911 * Read the entire EEPROM into the srom array 912 * 913 * Input parameters: 914 * sc - dp83815 state 915 ***************************************************************************/ 916 917static int 918eeprom_read_all(dp83815_softc *sc, uint8_t dest[]) 919{ 920 int i; 921 uint16_t cksum, temp; 922 923 WRITECSR(sc, R_MEAR, M_MEAR_EESEL); 924 925 eeprom_idle_state(sc); 926 927 for (i = 0; i < EEPROM_SIZE/2; i++) { 928 temp = eeprom_read_word(sc, i); 929 dest[2*i] = temp & 0xFF; 930 dest[2*i+1] = temp >> 8; 931 } 932 933 WRITECSR(sc, R_MEAR, 0); /* CS hold, Tcsh=0 */ 934 935 cksum = eeprom_checksum(dest);; 936 if (cksum != EEPROM_WORD(dest, EEPROM_CRC_INDEX)) { 937 xprintf("%s: Invalid EEPROM CHECKSUM, calc %04x, stored %04x\n", 938 dp83815_devname(sc), 939 cksum, EEPROM_WORD(dest, EEPROM_CRC_INDEX)); 940 return 0/*-1*/; 941 } 942 return 0; 943} 944 945static int 946eeprom_read_addr(const uint8_t rom[], uint8_t buf[]) 947{ 948 uint16_t s; 949 unsigned offset, mask; 950 int i, j; 951 952 if (eeprom_checksum(rom) != EEPROM_WORD(rom, EEPROM_SIZE-2)) 953 return -1; 954 955 s = 0; 956 offset = 2*6; mask = 0x1; 957 i = j = 0; 958 do { 959 s >>= 1; 960 if ((EEPROM_WORD(rom, offset) & mask) != 0) s |= 0x8000; 961 mask >>= 1; 962 if (mask == 0) { 963 offset +=2; mask = 0x8000; 964 } 965 i++; 966 if (i % 16 == 0) { 967 buf[j++] = s & 0xFF; 968 buf[j++] = s >> 8; 969 s = 0; 970 } 971 } while (i < ENET_ADDR_LEN*8); 972 973 return 0; 974} 975#endif /* MACPHYTER_TEST */ 976 977#if 0 978static void 979eeprom_dump(uint8_t srom[]) 980{ 981 int i; 982 983 xprintf("DP83815: EEPROM data:"); 984 for (i = 0; i < EEPROM_SIZE; i++) { 985 if (i % 16 == 0) 986 xprintf("\n %02x: ", i); 987 xprintf(" %02x", srom[i]); 988 } 989 xprintf("\n"); 990} 991#else 992#define eeprom_dump(srom) 993#endif 994 995 996static int 997dp83815_get_pm_addr(dp83815_softc *sc, uint8_t buf[]) 998{ 999#ifdef BCM47XX /* temporary patch */ 1000 /* The 47xx parts apparently have trouble accessing the RFDR 1001 register and get bus errors. For them, this function is a noop. 1002 The address passed into the probe routine is used instead, but 1003 since the station address is loaded into the PMATCH register, the 1004 two addresses must match for the MAC to receive unicast 1005 traffic. */ 1006 return -1; 1007#else 1008 uint32_t rfcr; 1009 unsigned rfaddr; 1010 unsigned i; 1011 uint32_t rfdata; 1012 1013 rfcr = READCSR(sc, R_RFCR); 1014 rfaddr = K_RFCR_PMATCH_ADDR; 1015 1016 for (i = 0; i < ENET_ADDR_LEN/2; i++) { 1017 rfcr &=~ M_RFCR_RFADDR; 1018 rfcr |= V_RFCR_RFADDR(rfaddr); 1019 WRITECSR(sc, R_RFCR, rfcr); 1020 rfdata = READCSR(sc, R_RFDR); 1021 buf[2*i] = rfdata & 0xFF; 1022 buf[2*i+1] = (rfdata >> 8) & 0xFF; 1023 rfaddr += 2; 1024 } 1025 1026 return 0; 1027#endif /* BCM47XX */ 1028} 1029 1030 1031#if MACPHYTER_TEST 1032/* MII access */ 1033 1034/* Current NICs use the internal PHY, which can be accessed more 1035 simply via internal registers. The following routines are 1036 primarily for management access to an external PHY and are retained 1037 for future applications. They have been tested on a Netgear FA311. */ 1038 1039/**************************************************************************** 1040 * MII access utility routines 1041 ***************************************************************************/ 1042 1043/* MII clock limited to 2.5 MHz (DP83815 allows 25 MHz), transactions 1044 end with MDIO tristated */ 1045 1046static void 1047mii_write_bits(dp83815_softc *sc, uint32_t data, unsigned int count) 1048{ 1049 uint32_t ctrl; 1050 uint32_t bitmask; 1051 1052 ctrl = READCSR(sc, R_MEAR) & ~M_MEAR_MDC; 1053 ctrl |= M_MEAR_MDDIR; 1054 1055 for (bitmask = 1 << (count-1); bitmask != 0; bitmask >>= 1) { 1056 ctrl &=~ M_MEAR_MDIO; 1057 if ((data & bitmask) != 0) ctrl |= M_MEAR_MDIO; 1058 WRITECSR(sc, R_MEAR, ctrl); 1059 1060 cfe_nsleep(2000); /* setup */ 1061 WRITECSR(sc, R_MEAR, ctrl | M_MEAR_MDC); 1062 cfe_nsleep(2000); /* hold */ 1063 WRITECSR(sc, R_MEAR, ctrl); 1064 } 1065} 1066 1067static void 1068mii_turnaround(dp83815_softc *sc) 1069{ 1070 uint32_t ctrl; 1071 1072 ctrl = READCSR(sc, R_MEAR) &~ M_MEAR_MDDIR; 1073 1074 /* stop driving data */ 1075 WRITECSR(sc, R_MEAR, ctrl); 1076 cfe_nsleep(2000); /* setup */ 1077 WRITECSR(sc, R_MEAR, ctrl | M_MEAR_MDC); 1078 cfe_nsleep(2000); /* clock high */ 1079 WRITECSR(sc, R_MEAR, ctrl); 1080 1081 /* read back and check for 0 here? */ 1082} 1083 1084/**************************************************************************** 1085 * mii_read_register 1086 * 1087 * This routine reads a register from the PHY chip using the MII 1088 * serial management interface. 1089 * 1090 * Input parameters: 1091 * index - index of register to read (0-31) 1092 * 1093 * Return value: 1094 * word read from register 1095 ***************************************************************************/ 1096 1097static uint16_t 1098mii_read_register(dp83815_softc *sc, unsigned int index) 1099{ 1100 /* Send the command and address to the PHY. The sequence is 1101 a synchronization sequence (32 1 bits) 1102 a "start" command (2 bits) 1103 a "read" command (2 bits) 1104 the PHY addr (5 bits) 1105 the register index (5 bits) 1106 */ 1107 uint32_t ctrl; 1108 uint16_t word; 1109 int i; 1110 1111 mii_write_bits(sc, 0xFF, 8); 1112 mii_write_bits(sc, 0xFFFFFFFF, 32); 1113 mii_write_bits(sc, MII_COMMAND_START, 2); 1114 mii_write_bits(sc, MII_COMMAND_READ, 2); 1115 mii_write_bits(sc, sc->phy_addr, 5); 1116 mii_write_bits(sc, index, 5); 1117 1118 mii_turnaround(sc); 1119 1120 ctrl = READCSR(sc, R_MEAR) &~ (M_MEAR_MDC | M_MEAR_MDDIR); 1121 word = 0; 1122 1123 for (i = 0; i < 16; i++) { 1124 WRITECSR(sc, R_MEAR, ctrl); 1125 cfe_nsleep(2000); /* clock width low */ 1126 WRITECSR(sc, R_MEAR, ctrl | M_MEAR_MDC); 1127 cfe_nsleep(2000); /* clock width high */ 1128 WRITECSR(sc, R_MEAR, ctrl); 1129 cfe_nsleep(1000); /* output delay */ 1130 word <<= 1; 1131 if ((READCSR(sc, R_MEAR) & M_MEAR_MDIO) != 0) 1132 word |= 0x0001; 1133 } 1134 1135 return word; 1136 1137 /* reset to output mode? */ 1138} 1139 1140/**************************************************************************** 1141 * mii_write_register 1142 * 1143 * This routine writes a register in the PHY chip using the MII 1144 * serial management interface. 1145 * 1146 * Input parameters: 1147 * index - index of register to write (0-31) 1148 * value - word to write 1149 ***************************************************************************/ 1150 1151static void 1152mii_write_register(dp83815_softc *sc, unsigned int index, uint16_t value) 1153{ 1154 mii_write_bits(sc, 0xFF, 8); 1155 mii_write_bits(sc, 0xFFFFFFFF, 32); 1156 mii_write_bits(sc, MII_COMMAND_START, 2); 1157 mii_write_bits(sc, MII_COMMAND_WRITE, 2); 1158 mii_write_bits(sc, sc->phy_addr, 5); 1159 mii_write_bits(sc, index, 5); 1160 mii_write_bits(sc, MII_COMMAND_ACK, 2); 1161 mii_write_bits(sc, value, 16); 1162 1163 /* reset to input mode? */ 1164} 1165 1166 1167static int 1168mii_probe(dp83815_softc *sc) 1169{ 1170 int i; 1171 uint16_t id1, id2; 1172 1173 /* Empirically, bit-banged access will return register 0 of the 1174 integrated PHY for all registers of all unpopulated PHY 1175 addresses. */ 1176 for (i = 0; i < 32; i++) { 1177 sc->phy_addr = i; 1178 id1 = mii_read_register(sc, MII_PHYIDR1); 1179 id2 = mii_read_register(sc, MII_PHYIDR2); 1180 if ((id1 != 0x0000 && id1 != 0xFFFF) || 1181 (id2 != 0x0000 && id2 != 0xFFFF)) { 1182 if (id1 != id2) { 1183 sc->phy_vendor = ((uint32_t)id1 << 6) | ((id2 >> 10) & 0x3F); 1184 sc->phy_device = (id2 >> 4) & 0x3F; 1185 return 0; 1186 } 1187 } 1188 } 1189 return -1; 1190} 1191 1192#if 0 1193static void 1194mii_dump(dp83815_softc *sc, const char *label) 1195{ 1196 int i; 1197 uint16_t r; 1198 1199 xprintf("%s\n", label); 1200 for (i = 0; i <= 6; ++i) { 1201 r = mii_read_register(sc, i); 1202 xprintf("MII_REG%02x: %04x\n", i, r); 1203 } 1204 if (sc->phy_vendor == OUI_NAT_SEMI && sc->phy_device == DEV_DP83815) { 1205 r = mii_read_register(sc, 7); 1206 xprintf("MII_REG%02x: %04x\n", i, r); 1207 for (i = 0x10; i <= 0x16; ++i) { 1208 r = mii_read_register(sc, i); 1209 xprintf("MII_REG%02x: %04x\n", i, r); 1210 } 1211 for (i = 0x19; i <= 0x1A; ++i) { 1212 r = mii_read_register(sc, i); 1213 xprintf("MII_REG%02x: %04x\n", i, r); 1214 } 1215 } 1216} 1217#else 1218#define mii_dump(sc,label) 1219#endif 1220 1221 1222/* The following functions are suitable for explicit MII access. */ 1223 1224static void 1225mii_set_speed(dp83815_softc *sc, int speed) 1226{ 1227 uint16_t control; 1228 1229 control = mii_read_register(sc, MII_BMCR); 1230 1231 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN); 1232 mii_write_register(sc, MII_BMCR, control); 1233 control &=~ (BMCR_SPEED0 | BMCR_SPEED1 | BMCR_DUPLEX); 1234 1235 switch (speed) { 1236 case ETHER_SPEED_10HDX: 1237 default: 1238 break; 1239 case ETHER_SPEED_10FDX: 1240 control |= BMCR_DUPLEX; 1241 break; 1242 case ETHER_SPEED_100HDX: 1243 control |= BMCR_SPEED100; 1244 break; 1245 case ETHER_SPEED_100FDX: 1246 control |= BMCR_SPEED100 | BMCR_DUPLEX ; 1247 break; 1248 } 1249 1250 mii_write_register(sc, MII_BMCR, control); 1251} 1252 1253static void 1254mii_autonegotiate(dp83815_softc *sc) 1255{ 1256 uint16_t control, status, cap; 1257 int timeout; 1258 int linkspeed; 1259 1260 linkspeed = ETHER_SPEED_UNKNOWN; 1261 1262 /* Read twice to clear latching bits */ 1263 status = mii_read_register(sc, MII_BMSR); 1264 status = mii_read_register(sc, MII_BMSR); 1265 mii_dump(sc, "query PHY"); 1266 1267 if ((status & (BMSR_AUTONEG | BMSR_LINKSTAT)) == 1268 (BMSR_AUTONEG | BMSR_LINKSTAT)) 1269 control = mii_read_register(sc, MII_BMCR); 1270 else { 1271 /* reset the PHY */ 1272 mii_write_register(sc, MII_BMCR, BMCR_RESET); 1273 timeout = 3*CFE_HZ; 1274 for (;;) { 1275 control = mii_read_register(sc, MII_BMCR); 1276 if ((control && BMCR_RESET) == 0 || timeout <= 0) 1277 break; 1278 cfe_sleep(CFE_HZ/2); 1279 timeout -= CFE_HZ/2; 1280 } 1281 if ((control & BMCR_RESET) != 0) { 1282 xprintf("%s: PHY reset failed\n", dp83815_devname(sc)); 1283 return; 1284 } 1285 1286 status = mii_read_register(sc, MII_BMSR); 1287 cap = ((status >> 6) & (ANAR_TXFD | ANAR_TXHD | ANAR_10FD | ANAR_10HD)) 1288 | PSB_802_3; 1289 mii_write_register(sc, MII_ANAR, cap); 1290 control |= (BMCR_ANENABLE | BMCR_RESTARTAN); 1291 mii_write_register(sc, MII_BMCR, control); 1292 1293 timeout = 3*CFE_HZ; 1294 for (;;) { 1295 status = mii_read_register(sc, MII_BMSR); 1296 if ((status & BMSR_ANCOMPLETE) != 0 || timeout <= 0) 1297 break; 1298 cfe_sleep(CFE_HZ/2); 1299 timeout -= CFE_HZ/2; 1300 } 1301 mii_dump(sc, "done PHY"); 1302 } 1303 1304 xprintf("%s: Link speed: ", dp83815_devname(sc)); 1305 if ((status & BMSR_ANCOMPLETE) != 0) { 1306 /* A link partner was negogiated... */ 1307 1308 uint16_t remote = mii_read_register(sc, MII_ANLPAR); 1309 1310 if ((remote & ANLPAR_TXFD) != 0) { 1311 xprintf("100BaseT FDX\n"); 1312 linkspeed = ETHER_SPEED_100FDX; 1313 } 1314 else if ((remote & ANLPAR_TXHD) != 0) { 1315 xprintf("100BaseT HDX\n"); 1316 linkspeed = ETHER_SPEED_100HDX; 1317 } 1318 else if ((remote & ANLPAR_10FD) != 0) { 1319 xprintf("10BaseT FDX\n"); 1320 linkspeed = ETHER_SPEED_10FDX; 1321 } 1322 else if ((remote & ANLPAR_10HD) != 0) { 1323 xprintf("10BaseT HDX\n"); 1324 linkspeed = ETHER_SPEED_10HDX; 1325 } 1326 } 1327 else { 1328 /* no link partner negotiation */ 1329 control &=~ (BMCR_ANENABLE | BMCR_RESTARTAN); 1330 mii_write_register(sc, MII_BMCR, control); 1331 xprintf("10BaseT HDX (assumed)\n"); 1332 linkspeed = ETHER_SPEED_10HDX; 1333 if ((status & BMSR_LINKSTAT) == 0) 1334 mii_write_register(sc, MII_BMCR, control); 1335 mii_set_speed(sc, linkspeed); 1336 } 1337 1338 status = mii_read_register(sc, MII_BMSR); /* clear latching bits */ 1339 mii_dump(sc, "final PHY"); 1340} 1341#endif /* MACPHYTER_TEST */ 1342 1343 1344static void 1345dp83815_phyupdate(dp83815_softc *sc, uint32_t status) 1346{ 1347 xprintf("%s: Link speed: ", dp83815_devname(sc)); 1348 if ((status & M_CFG_LNKSTS) != 0) { 1349 switch (status & (M_CFG_SPEED100 | M_CFG_FDUP)) { 1350 case (M_CFG_SPEED100 | M_CFG_FDUP): 1351 sc->linkspeed = ETHER_SPEED_100FDX; 1352 xprintf("100BaseT FDX\n"); 1353 break; 1354 case (M_CFG_SPEED100): 1355 sc->linkspeed = ETHER_SPEED_100HDX; 1356 xprintf("100BaseT HDX\n"); 1357 break; 1358 case (M_CFG_FDUP): 1359 sc->linkspeed = ETHER_SPEED_10FDX; 1360 xprintf("10BaseT FDX\n"); 1361 break; 1362 default: 1363 sc->linkspeed = ETHER_SPEED_10HDX; 1364 xprintf("10BaseT HDX\n"); 1365 break; 1366 } 1367 if ((status & M_CFG_SPEED100) != 0) { 1368 uint32_t t; 1369 1370 /* This is a reputed fix that improves 100BT rx 1371 performance on short cables with "a small number" 1372 of DP83815 chips. It comes from Bruce at NatSemi 1373 via the Soekris support web page (see appended 1374 note). */ 1375 1376 WRITECSR(sc, R_PGSEL, 0x0001); 1377 (void)READCSR(sc, R_PGSEL); /* push */ 1378 t = READCSR(sc, R_DSPCFG); 1379 WRITECSR(sc, R_DSPCFG, (t & 0xFFF) | 0x1000); 1380 cfe_sleep(1); 1381 t = READCSR(sc, R_TSTDAT) & 0xFF; 1382 if ((t & 0x0080) == 0 || ((t > 0x00D8) && (t <= 0x00FF))) { 1383 WRITECSR(sc, R_TSTDAT, 0x00E8); 1384 t = READCSR(sc, R_DSPCFG); 1385 WRITECSR(sc, R_DSPCFG, t | 0x0020); 1386 } 1387 WRITECSR(sc, R_PGSEL, 0); 1388 } 1389 if ((status & M_CFG_FDUP) != (sc->phy_status & M_CFG_FDUP)) { 1390 uint32_t txcfg, rxcfg; 1391 1392 txcfg = READCSR(sc, R_TXCFG); 1393 rxcfg = READCSR(sc, R_RXCFG); 1394 if (status & M_CFG_FDUP) { 1395 txcfg |= (M_TXCFG_CSI | M_TXCFG_HBI); 1396 rxcfg |= M_RXCFG_ATX; 1397 } 1398 else { 1399 txcfg &= ~(M_TXCFG_CSI | M_TXCFG_HBI); 1400 rxcfg &= ~M_RXCFG_ATX; 1401 } 1402 WRITECSR(sc, R_TXCFG, txcfg); 1403 WRITECSR(sc, R_RXCFG, rxcfg); 1404 } 1405 } 1406 else { 1407 xprintf("Unknown\n"); 1408 } 1409 1410 sc->phy_status = status; 1411} 1412 1413static void 1414dp83815_hwinit(dp83815_softc *sc) 1415{ 1416 if (sc->state == eth_state_uninit) { 1417 uint32_t cfg; 1418 uint32_t txcfg, rxcfg; 1419 uint32_t ready; 1420 int timeout; 1421 1422 /* RESET_ADAPTER(sc); */ 1423 sc->state = eth_state_off; 1424 sc->bus_errors = 0; 1425 1426 cfg = READCSR(sc, R_CFG); 1427#if ENDIAN_BIG 1428 cfg |= M_CFG_BEM; /* We will use match bits */ 1429#endif 1430 WRITECSR(sc, R_CFG, cfg); 1431 1432 sc->phy_status = 0; 1433 dp83815_phyupdate(sc, cfg & M_CFG_LNKSUMMARY); 1434 1435 /* Set a maximum tx DMA burst length of 512 (128*4) bytes, a 1436 fill threshold of 512 (16*32) and a drain threshold of 64 1437 (2*32) bytes. */ 1438 txcfg = READCSR(sc, R_TXCFG); 1439 txcfg &= ~(M_TXCFG_MXDMA | M_TXCFG_FLTH | M_TXCFG_DRTH); 1440 txcfg |= (M_TXCFG_ATP 1441 | V_TXCFG_MXDMA(K_MXDMA_512) 1442 | V_TXCFG_FLTH(16) | V_TXCFG_DRTH(2)); 1443 WRITECSR(sc, R_TXCFG, txcfg); 1444 1445 /* Set a maximum rx DMA burst length of 512 (128*4) bytes, and 1446 an rx drain threshhold of 128 (16*8) bytes */ 1447 rxcfg = READCSR(sc, R_RXCFG); 1448 rxcfg &= ~(M_RXCFG_MXDMA | M_RXCFG_DRTH); 1449 rxcfg |= (V_RXCFG_MXDMA(K_MXDMA_512) | V_RXCFG_DRTH(16)); 1450 WRITECSR(sc, R_RXCFG, rxcfg); 1451 1452#if MACPHYTER_TEST 1453 { 1454 uint8_t srom[EEPROM_SIZE]; 1455 uint8_t addr[ENET_ADDR_LEN]; 1456 1457 eeprom_read_all(sc, srom); 1458 eeprom_dump(srom); 1459 xprintf(" checksum %04x\n", eeprom_checksum(srom)); 1460 if (eeprom_read_addr(srom, addr) == 0) 1461 xprintf(" addr: %02x-%02x-%02x-%02x-%02x-%02x\n", 1462 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1463 1464 mii_probe(sc); 1465 xprintf("MII address %02x\n", sc->phy_addr); 1466 mii_dump(sc, "DP83815 PHY:"); 1467 (void)mii_autonegotiate; 1468 } 1469#endif /* MACPHYTER_TEST */ 1470 1471 /* XXX fix up rx filtering here. We are relying on the EEPROM. */ 1472 1473 /* XXX This is inappropriate on a restart. */ 1474 timeout = 2*CFE_HZ; 1475 ready = 0; 1476 for (;;) { 1477 ready |= READCSR(sc, R_ISR); 1478 if ((ready & (M_INT_TXRCMP | M_INT_RXRCMP)) 1479 == (M_INT_TXRCMP | M_INT_RXRCMP) || timeout <= 0) 1480 break; 1481 cfe_sleep(CFE_HZ/10); 1482 timeout -= CFE_HZ/10; 1483 } 1484 if ((ready & M_INT_TXRCMP) == 0) 1485 xprintf("%s: tx reset failed\n", dp83815_devname(sc)); 1486 if ((ready & M_INT_RXRCMP) == 0) 1487 xprintf("%s: rx reset failed\n", dp83815_devname(sc)); 1488 } 1489} 1490 1491static void 1492dp83815_setspeed(dp83815_softc *sc, int speed) 1493{ 1494 /* XXX Not yet implemented - autonegotiation only. */ 1495} 1496 1497static void 1498dp83815_setloopback(dp83815_softc *sc, int mode) 1499{ 1500 /* XXX Not yet implemented. */ 1501} 1502 1503 1504static void 1505dp83815_isr(void *arg) 1506{ 1507 dp83815_softc *sc = (dp83815_softc *)arg; 1508 uint32_t status; 1509 uint32_t isr; 1510 1511#if IPOLL 1512 sc->interrupts++; 1513#endif 1514 1515 for (;;) { 1516 1517 /* Read (and clear) the interrupt status. */ 1518 isr = READCSR(sc, R_ISR); 1519 status = isr & sc->intmask; 1520 1521 /* if there are no more interrupts, leave now. */ 1522 if (status == 0) break; 1523 1524 /* Now, test each unmasked bit in the interrupt register and 1525 handle each interrupt type appropriately. */ 1526 1527 if (status & (M_INT_RTABT | M_INT_RMABT)) { 1528 WRITECSR(sc, R_IER, 0); 1529 1530 xprintf("%s: bus error %08x\n", dp83815_devname(sc), status); 1531 dumpstat(sc); 1532 sc->bus_errors++; 1533 if (sc->bus_errors >= 2) { 1534 dumpcsrs(sc); 1535 RESET_ADAPTER(sc); 1536 sc->state = eth_state_off; 1537 sc->bus_errors = 0; 1538 } 1539#if IPOLL 1540 else 1541 WRITECSR(sc, R_IMR, sc->intmask); 1542#endif 1543 } 1544 1545 if (status & M_INT_RXDESC) { 1546#if IPOLL 1547 sc->rx_interrupts++; 1548#endif 1549 dp83815_procrxring(sc); 1550 } 1551 1552 if (status & M_INT_TXDESC) { 1553#if IPOLL 1554 sc->tx_interrupts++; 1555#endif 1556 dp83815_proctxring(sc); 1557 } 1558 1559 if (status & (M_INT_TXURN | M_INT_RXORN)) { 1560 if (status & M_INT_TXURN) { 1561 xprintf("%s: tx underrun, %08x\n", dp83815_devname(sc), isr); 1562 /* XXX Try to restart */ 1563 } 1564 if (status & M_INT_RXORN) { 1565 xprintf("%s: tx overrun, %08x\n", dp83815_devname(sc), isr); 1566 /* XXX Try to restart */ 1567 } 1568 } 1569 1570 if (status & M_INT_PHY) { 1571 sc->intmask &= ~ M_INT_PHY; 1572 WRITECSR(sc, R_IMR, sc->intmask); 1573 (void)READCSR(sc, R_MISR); /* Clear at PHY */ 1574 sc->phy_check = 1; 1575 } 1576 1577 } 1578} 1579 1580static void 1581dp83815_checkphy(dp83815_softc *sc) 1582{ 1583 uint32_t cfg; 1584 uint32_t status; 1585 1586 (void)READCSR(sc, R_MISR); /* Clear at PHY */ 1587 cfg = READCSR(sc, R_CFG); 1588 status = cfg & M_CFG_LNKSUMMARY; 1589 if (status != sc->phy_status) { 1590 /* XXX Can we really do the phy update with active rx and tx? */ 1591 dp83815_phyupdate(sc, status); 1592 } 1593 1594 sc->intmask |= M_INT_PHY; 1595 WRITECSR(sc, R_IMR, sc->intmask); 1596} 1597 1598 1599static void 1600dp83815_start(dp83815_softc *sc) 1601{ 1602 dp83815_hwinit(sc); 1603 1604 /* Set up loopback here */ 1605 1606 sc->intmask = 0; 1607 WRITECSR(sc, R_IER, 0); /* no interrupts */ 1608 WRITECSR(sc, R_IMR, 0); 1609 (void)READCSR(sc, R_ISR); /* clear any pending */ 1610 1611 sc->phy_status = READCSR(sc, R_CFG) & M_CFG_LNKSUMMARY; 1612 sc->phy_check = 0; 1613 1614 sc->intmask = M_INT_RXDESC | M_INT_TXDESC; 1615 sc->intmask |= M_INT_RTABT | M_INT_RMABT | M_INT_RXORN | M_INT_TXURN; 1616 sc->intmask |= M_INT_PHY; 1617 1618#if IPOLL 1619 cfe_request_irq(sc->irq, dp83815_isr, sc, CFE_IRQ_FLAGS_SHARED, 0); 1620 WRITECSR(sc, R_IMR, sc->intmask); 1621 WRITECSR(sc, R_IER, M_IER_IE); 1622#endif 1623 1624 (void)READCSR(sc, R_MISR); /* clear any pending */ 1625 WRITECSR(sc, R_MISR, MISR_MSKJAB | MISR_MSKRF | MISR_MSKFHF | MISR_MSKRHF); 1626 WRITECSR(sc, R_MICR, MICR_INTEN); 1627 1628 WRITECSR(sc, R_TXDP, PTR_TO_PCI(sc->txdscr_start)); 1629 WRITECSR(sc, R_RXDP, PTR_TO_PCI(sc->rxdscr_start)); 1630 1631 WRITECSR(sc, R_MIBC, M_MIBC_ACLR); /* zero hw MIB counters */ 1632 1633 WRITECSR(sc, R_CR, M_CR_TXE | M_CR_RXE); 1634 sc->state = eth_state_on; 1635} 1636 1637static void 1638dp83815_stop(dp83815_softc *sc) 1639{ 1640 uint32_t status; 1641 int count; 1642 1643 /* Make sure that no further interrutps will be processed. */ 1644 sc->intmask = 0; 1645 WRITECSR(sc, R_IER, 0); 1646 WRITECSR(sc, R_IMR, 0); 1647 1648#if IPOLL 1649 (void)READCSR(sc, R_IER); /* Push */ 1650 cfe_free_irq(sc->irq, 0); 1651#endif 1652 1653 WRITECSR(sc, R_CR, M_CR_TXD | M_CR_RXD); 1654 1655 /* wait for any DMA activity to terminate */ 1656 for (count = 0; count <= 13; count++) { 1657 status = READCSR(sc, R_CR); 1658 if ((status & (M_CR_TXE | M_CR_RXE)) == 0) 1659 break; 1660 cfe_sleep(CFE_HZ/10); 1661 } 1662 if (count > 13) { 1663 xprintf("%s: idle state not achieved\n", dp83815_devname(sc)); 1664 dumpstat(sc); 1665 RESET_ADAPTER(sc); 1666 sc->state = eth_state_uninit; 1667#if 1 1668 sc->linkspeed = ETHER_SPEED_AUTO; 1669#endif 1670 } 1671#if 0 /* XXX Not yet implemented. */ 1672 else if (sc->loopback != ETHER_LOOPBACK_OFF) { 1673 dp83815_setloopback(sc, ETHER_LOOPBACK_OFF); 1674 } 1675#endif 1676 1677 (void)READCSR(sc, R_ISR); /* Clear any stragglers. */ 1678} 1679 1680 1681/* ********************************************************************* 1682 * Declarations for CFE Device Driver Interface routines 1683 ********************************************************************* */ 1684 1685static int dp83815_ether_open(cfe_devctx_t *ctx); 1686static int dp83815_ether_read(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1687static int dp83815_ether_inpstat(cfe_devctx_t *ctx,iocb_inpstat_t *inpstat); 1688static int dp83815_ether_write(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1689static int dp83815_ether_ioctl(cfe_devctx_t *ctx,iocb_buffer_t *buffer); 1690static int dp83815_ether_close(cfe_devctx_t *ctx); 1691static void dp83815_ether_poll(cfe_devctx_t *ctx, int64_t ticks); 1692static void dp83815_ether_reset(void *softc); 1693 1694/* ********************************************************************* 1695 * CFE Device Driver dispatch structure 1696 ********************************************************************* */ 1697 1698const static cfe_devdisp_t dp83815_ether_dispatch = { 1699 dp83815_ether_open, 1700 dp83815_ether_read, 1701 dp83815_ether_inpstat, 1702 dp83815_ether_write, 1703 dp83815_ether_ioctl, 1704 dp83815_ether_close, 1705 dp83815_ether_poll, 1706 dp83815_ether_reset 1707}; 1708 1709/* ********************************************************************* 1710 * CFE Device Driver descriptor 1711 ********************************************************************* */ 1712 1713const cfe_driver_t dp83815drv = { 1714 "DP83815 Ethernet", 1715 "eth", 1716 CFE_DEV_NETWORK, 1717 &dp83815_ether_dispatch, 1718 dp83815_ether_probe 1719}; 1720 1721 1722static int 1723dp83815_ether_attach(cfe_driver_t *drv, pcitag_t tag, uint8_t hwaddr[]) 1724{ 1725 dp83815_softc *sc; 1726 uint32_t device; 1727 uint32_t class; 1728 phys_addr_t pa; 1729 uint8_t promaddr[ENET_ADDR_LEN]; 1730 char descr[100]; 1731 uint32_t srr; 1732 1733 device = pci_conf_read(tag, R_CFGID); 1734 class = pci_conf_read(tag, R_CFGRID); 1735 1736#if 1 1737 /* Use memory space for the CSRs */ 1738 pci_map_mem(tag, R_CFGMA, PCI_MATCH_BITS, &pa); 1739#else 1740 /* Use i/o space for the CSRs */ 1741 pci_map_io(tag, R_CFGIOA, PCI_MATCH_BITS, &pa); 1742#endif 1743 1744 sc = (dp83815_softc *) KMALLOC(sizeof(dp83815_softc), 0); 1745 1746 if (sc == NULL) { 1747 xprintf("DP83815: No memory to complete probe\n"); 1748 return 0; 1749 } 1750 memset(sc, 0, sizeof(*sc)); 1751 1752 sc->membase = (uint32_t)pa; 1753 sc->irq = pci_conf_read(tag, R_CFGINT) & 0xFF; 1754 sc->tag = tag; 1755 sc->device = PCI_PRODUCT(device); 1756 sc->revision = PCI_REVISION(class); 1757 sc->devctx = NULL; 1758 1759#if 1 1760 sc->linkspeed = ETHER_SPEED_AUTO; /* select autonegotiation */ 1761#else 1762 sc->linkspeed = ETHER_SPEED_100FDX; /* 100 Mbps, full duplex */ 1763#endif 1764 sc->loopback = ETHER_LOOPBACK_OFF; 1765 memcpy(sc->hwaddr, hwaddr, ENET_ADDR_LEN); 1766 1767 srr = READCSR(sc, R_SRR); 1768#if 0 1769 /* The NS data sheet recommends the following for "optimal 1770 performance" of CVNG parts. Tested on a sample of one CVNG 1771 part on an NS "Macphyter Demo II" eval board, it seemed to 1772 produce slightly less reliable initial behavior. */ 1773 if (G_SRR_REV(srr) == K_REV_CVNG) { 1774 /* Update PHY DSP registers per data sheet. */ 1775 WRITECSR(sc, R_PGSEL, 0x0001); 1776 (void)READCSR(sc, R_PGSEL); /* push */ 1777 WRITECSR(sc, R_PMDCSR, 0x189C); 1778 WRITECSR(sc, R_TSTDAT, 0x0000); 1779 WRITECSR(sc, R_DSPCFG, 0x5040); 1780 WRITECSR(sc, R_SDCFG, 0x008C); 1781 } 1782#endif 1783 1784 dp83815_init(sc); 1785 1786 /* Prefer the address in EEPROM. This will be read into the 1787 PMATCH register upon power up. Unfortunately, how to test for 1788 completion of the auto-load (but see PTSCR_EELOAD_EN). */ 1789 if (dp83815_get_pm_addr(sc, promaddr) == 0) { 1790 memcpy(sc->hwaddr, promaddr, ENET_ADDR_LEN); 1791 } 1792 1793 sc->state = eth_state_uninit; 1794 1795 xsprintf(descr, "%s at 0x%X (%02x-%02x-%02x-%02x-%02x-%02x)", 1796 drv->drv_description, sc->membase, 1797 sc->hwaddr[0], sc->hwaddr[1], sc->hwaddr[2], 1798 sc->hwaddr[3], sc->hwaddr[4], sc->hwaddr[5]); 1799 1800 cfe_attach(drv, sc, NULL, descr); 1801 return 1; 1802} 1803 1804 1805/* ********************************************************************* 1806 * DP83815_ETHER_PROBE(drv,probe_a,probe_b,probe_ptr) 1807 * 1808 * Probe and install drivers for all dp83815 Ethernet controllers. 1809 * For each, create a context structure and attach to the 1810 * specified network device. 1811 * 1812 * Input parameters: 1813 * drv - driver descriptor 1814 * probe_a - not used 1815 * probe_b - not used 1816 * probe_ptr - string pointer to hardware address for the first 1817 * MAC, in the form xx:xx:xx:xx:xx:xx 1818 * 1819 * Return value: 1820 * nothing 1821 ********************************************************************* */ 1822static void 1823dp83815_ether_probe(cfe_driver_t *drv, 1824 unsigned long probe_a, unsigned long probe_b, 1825 void *probe_ptr) 1826{ 1827 int n; 1828 uint8_t hwaddr[ENET_ADDR_LEN]; 1829 1830 if (probe_ptr) 1831 enet_parse_hwaddr((char *) probe_ptr, hwaddr); 1832 else { 1833 /* use default address 02-00-00-10-0B-00 */ 1834 hwaddr[0] = 0x02; hwaddr[1] = 0x00; hwaddr[2] = 0x00; 1835 hwaddr[3] = 0x10; hwaddr[4] = 0x0B; hwaddr[5] = 0x00; 1836 } 1837 1838 n = 0; 1839 for (;;) { 1840 pcitag_t tag; 1841 1842 if (pci_find_device(K_PCI_VENDOR_NSC, K_PCI_ID_DP83815, n, &tag) != 0) 1843 break; 1844 dp83815_ether_attach(drv, tag, hwaddr); 1845 n++; 1846 enet_incr_hwaddr(hwaddr, 1); 1847 } 1848} 1849 1850 1851/* The functions below are called via the dispatch vector for the 83815. */ 1852 1853/* ********************************************************************* 1854 * DP83815_ETHER_OPEN(ctx) 1855 * 1856 * Open the Ethernet device. The MAC is reset, initialized, and 1857 * prepared to receive and send packets. 1858 * 1859 * Input parameters: 1860 * ctx - device context (includes ptr to our softc) 1861 * 1862 * Return value: 1863 * status, 0 = ok 1864 ********************************************************************* */ 1865static int 1866dp83815_ether_open(cfe_devctx_t *ctx) 1867{ 1868 dp83815_softc *sc = ctx->dev_softc; 1869 1870 if (sc->state == eth_state_on) 1871 dp83815_stop(sc); 1872 1873 sc->devctx = ctx; 1874 1875 sc->inpkts = sc->outpkts = 0; 1876 sc->interrupts = 0; 1877 sc->rx_interrupts = sc->tx_interrupts = 0; 1878 1879 dp83815_start(sc); 1880 1881#if XPOLL 1882 dp83815_isr(sc); 1883#endif 1884 1885 return 0; 1886} 1887 1888/* ********************************************************************* 1889 * DP83815_ETHER_READ(ctx,buffer) 1890 * 1891 * Read a packet from the Ethernet device. If no packets are 1892 * available, the read will succeed but return 0 bytes. 1893 * 1894 * Input parameters: 1895 * ctx - device context (includes ptr to our softc) 1896 * buffer - pointer to buffer descriptor. 1897 * 1898 * Return value: 1899 * status, 0 = ok 1900 ********************************************************************* */ 1901static int 1902dp83815_ether_read(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 1903{ 1904 dp83815_softc *sc = ctx->dev_softc; 1905 eth_pkt_t *pkt; 1906 int blen; 1907 1908#if XPOLL 1909 dp83815_isr(sc); 1910#endif 1911 1912 if (sc->state != eth_state_on) return -1; 1913 1914 CS_ENTER(sc); 1915 pkt = (eth_pkt_t *) q_deqnext(&(sc->rxqueue)); 1916 CS_EXIT(sc); 1917 1918 if (pkt == NULL) { 1919 buffer->buf_retlen = 0; 1920 return 0; 1921 } 1922 1923 blen = buffer->buf_length; 1924 if (blen > pkt->length) blen = pkt->length; 1925 1926 CACHE_DMA_INVAL(pkt->buffer, blen); 1927 hs_memcpy_to_hs(buffer->buf_ptr, pkt->buffer, blen); 1928 buffer->buf_retlen = blen; 1929 1930 eth_free_pkt(sc, pkt); 1931 dp83815_fillrxring(sc); 1932 1933#if XPOLL 1934 dp83815_isr(sc); 1935#endif 1936 1937 return 0; 1938} 1939 1940/* ********************************************************************* 1941 * DP83815_ETHER_INPSTAT(ctx,inpstat) 1942 * 1943 * Check for received packets on the Ethernet device 1944 * 1945 * Input parameters: 1946 * ctx - device context (includes ptr to our softc) 1947 * inpstat - pointer to input status structure 1948 * 1949 * Return value: 1950 * status, 0 = ok 1951 ********************************************************************* */ 1952static int 1953dp83815_ether_inpstat(cfe_devctx_t *ctx, iocb_inpstat_t *inpstat) 1954{ 1955 dp83815_softc *sc = ctx->dev_softc; 1956 1957#if XPOLL 1958 dp83815_isr(sc); 1959#endif 1960 1961 if (sc->state != eth_state_on) return -1; 1962 1963 /* We avoid an interlock here because the result is a hint and an 1964 interrupt cannot turn a non-empty queue into an empty one. */ 1965 inpstat->inp_status = (q_isempty(&(sc->rxqueue))) ? 0 : 1; 1966 1967 return 0; 1968} 1969 1970/* ********************************************************************* 1971 * DP83815_ETHER_WRITE(ctx,buffer) 1972 * 1973 * Write a packet to the Ethernet device. 1974 * 1975 * Input parameters: 1976 * ctx - device context (includes ptr to our softc) 1977 * buffer - pointer to buffer descriptor. 1978 * 1979 * Return value: 1980 * status, 0 = ok 1981 ********************************************************************* */ 1982static int 1983dp83815_ether_write(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 1984{ 1985 dp83815_softc *sc = ctx->dev_softc; 1986 eth_pkt_t *pkt; 1987 int blen; 1988 1989#if XPOLL 1990 dp83815_isr(sc); 1991#endif 1992 1993 if (sc->state != eth_state_on) return -1; 1994 1995 pkt = eth_alloc_pkt(sc); 1996 if (!pkt) return CFE_ERR_NOMEM; 1997 1998 blen = buffer->buf_length; 1999 if (blen > pkt->length) blen = pkt->length; 2000 2001 hs_memcpy_from_hs(pkt->buffer, buffer->buf_ptr, blen); 2002 pkt->length = blen; 2003 2004 CACHE_DMA_SYNC(pkt->buffer, blen); 2005 if (dp83815_transmit(sc, pkt) != 0) { 2006 eth_free_pkt(sc,pkt); 2007 return CFE_ERR_IOERR; 2008 } 2009 2010#if XPOLL 2011 dp83815_isr(sc); 2012#endif 2013 2014 return 0; 2015} 2016 2017/* ********************************************************************* 2018 * DP83815_ETHER_IOCTL(ctx,buffer) 2019 * 2020 * Do device-specific I/O control operations for the device 2021 * 2022 * Input parameters: 2023 * ctx - device context (includes ptr to our softc) 2024 * buffer - pointer to buffer descriptor. 2025 * 2026 * Return value: 2027 * status, 0 = ok 2028 ********************************************************************* */ 2029static int 2030dp83815_ether_ioctl(cfe_devctx_t *ctx, iocb_buffer_t *buffer) 2031{ 2032 dp83815_softc *sc = ctx->dev_softc; 2033 int mode; 2034 int speed; 2035 2036 switch ((int)buffer->buf_ioctlcmd) { 2037 case IOCTL_ETHER_GETHWADDR: 2038 hs_memcpy_to_hs(buffer->buf_ptr, sc->hwaddr, sizeof(sc->hwaddr)); 2039 return 0; 2040 2041 case IOCTL_ETHER_SETHWADDR: 2042 return -1; /* not supported */ 2043 2044 case IOCTL_ETHER_GETSPEED: 2045 speed = sc->linkspeed; 2046 hs_memcpy_to_hs(buffer->buf_ptr,&speed,sizeof(int)); 2047 return 0; 2048 2049 case IOCTL_ETHER_SETSPEED: 2050 dp83815_stop(sc); 2051 dp83815_resetrings(sc); 2052 hs_memcpy_from_hs(&speed,buffer->buf_ptr,sizeof(int)); 2053 dp83815_setspeed(sc, speed); 2054 dp83815_start(sc); 2055 sc->state = eth_state_on; 2056 return 0; 2057 2058 case IOCTL_ETHER_GETLINK: 2059 mode = sc->linkspeed; 2060 hs_memcpy_to_hs(buffer->buf_ptr,&mode,sizeof(int)); 2061 return 0; 2062 2063 case IOCTL_ETHER_GETLOOPBACK: 2064 mode = sc->loopback; 2065 hs_memcpy_to_hs(buffer->buf_ptr,&mode,sizeof(int)); 2066 return 0; 2067 2068 case IOCTL_ETHER_SETLOOPBACK: 2069 dp83815_stop(sc); 2070 dp83815_resetrings(sc); 2071 hs_memcpy_from_hs(&mode,buffer->buf_ptr,sizeof(int)); 2072 sc->loopback = ETHER_LOOPBACK_OFF; /* default */ 2073 if (mode == ETHER_LOOPBACK_INT || mode == ETHER_LOOPBACK_EXT) { 2074 dp83815_setloopback(sc, mode); 2075 } 2076 dp83815_start(sc); 2077 sc->state = eth_state_on; 2078 return 0; 2079 2080 default: 2081 return -1; 2082 } 2083} 2084 2085/* ********************************************************************* 2086 * DP83815_ETHER_CLOSE(ctx) 2087 * 2088 * Close the Ethernet device. 2089 * 2090 * Input parameters: 2091 * ctx - device context (includes ptr to our softc) 2092 * 2093 * Return value: 2094 * status, 0 = ok 2095 ********************************************************************* */ 2096static int 2097dp83815_ether_close(cfe_devctx_t *ctx) 2098{ 2099 dp83815_softc *sc = ctx->dev_softc; 2100 2101 sc->state = eth_state_off; 2102 dp83815_stop(sc); 2103 2104 /* resynchronize descriptor rings */ 2105 dp83815_resetrings(sc); 2106 2107 xprintf("%s: %d sent, %d received, %d interrupts\n", 2108 dp83815_devname(sc), sc->outpkts, sc->inpkts, sc->interrupts); 2109 if (IPOLL) { 2110 xprintf(" %d rx interrupts, %d tx interrupts\n", 2111 sc->rx_interrupts, sc->tx_interrupts); 2112 } 2113 2114 sc->devctx = NULL; 2115 return 0; 2116} 2117 2118 2119/* ********************************************************************* 2120 * DP83815_ETHER_POLL(ctx,ticks) 2121 * 2122 * TBD 2123 * 2124 * Input parameters: 2125 * ctx - device context (includes ptr to our softc) 2126 * ticks- current time in ticks 2127 * 2128 * Return value: 2129 * nothing 2130 ********************************************************************* */ 2131 2132static void 2133dp83815_ether_poll(cfe_devctx_t *ctx, int64_t ticks) 2134{ 2135 dp83815_softc *sc = ctx->dev_softc; 2136 2137 if (sc->phy_check) { 2138 sc->phy_check = 0; 2139 dp83815_checkphy(sc); 2140 } 2141} 2142 2143 2144/* ********************************************************************* 2145 * DP83815_ETHER_RESET(softc) 2146 * 2147 * This routine is called when CFE is restarted after a 2148 * program exits. We can clean up pending I/Os here. 2149 * 2150 * Input parameters: 2151 * softc - pointer to dp83815_softc 2152 * 2153 * Return value: 2154 * nothing 2155 ********************************************************************* */ 2156 2157static void 2158dp83815_ether_reset(void *softc) 2159{ 2160 dp83815_softc *sc = (dp83815_softc *)softc; 2161 2162 /* Turn off the Ethernet interface. */ 2163 2164 /* RESET_ADAPTER(sc); */ 2165 2166 sc->state = eth_state_uninit; 2167} 2168