Searched refs:PHYS_TO_K1 (Results 1 - 25 of 59) sorted by relevance

123

/broadcom-cfe-1.4.2/cfe/arch/mips/common/include/
H A Daddrspace.h63 #define KERNADDR(x) PHYS_TO_K1(x)
66 #define UNCADDR(x) PHYS_TO_K1(x)
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125pcix/src/
H A Dbcm91125pcix_init.S109 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
113 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
122 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
144 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
167 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(USB1_CS))
188 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(USB2_CS))
209 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(PCMCIA_CS))
230 li t0,PHYS_TO_K1(A_DUART_MODE_REG_1_A)
236 li t0,PHYS_TO_K1(A_DUART_MODE_REG_2_A)
242 li t0,PHYS_TO_K1(A_DUART_CLK_SEL_
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125e/src/
H A Dbcm91125e_init.S110 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
114 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
121 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
129 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
150 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
173 ld t1, PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
188 ld t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
191 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* clear soft reset */
196 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* go unicpu */
206 li t0, PHYS_TO_K1(A_MC_BASE_
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125f/src/
H A Dbcm91125f_init.S110 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
114 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
121 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
129 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
148 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(BOOTROM_CS))
161 ld t1, PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
176 ld t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
179 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* clear soft reset */
184 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* go unicpu */
194 li t0, PHYS_TO_K1(A_MC_BASE_
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480b/src/
H A Dbcm91480b_init.S120 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
124 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
132 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
136 li t0,PHYS_TO_K1(A_GPIO_PIN_SET)
144 li t0,PHYS_TO_K1(A_IO_PCMCIA_CFG)
159 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_LO(0x00))
161 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_HI(0x08))
175 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
179 li t0,PHYS_TO_K1(A_GPIO_PIN_SET)
188 li t0,PHYS_TO_K1(A_IO_EXT_CS_BAS
[all...]
/broadcom-cfe-1.4.2/cfe/dev/
H A Ddev_atapi.c103 return *((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr));
108 return *((volatile uint16_t *) PHYS_TO_K1((reg+disp->baseaddr)));
116 data = *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr));
133 *((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr)) = val;
139 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = val;
154 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = data;
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91280e/src/
H A Dbcm91280e_init.S122 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
126 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
136 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_LO(0x00))
138 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_HI(0x08))
152 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
173 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
193 li t0,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_0_CLR_CPU))
196 li t0,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_1_CLR_CPU))
203 li t0,PHYS_TO_K1(A_DUART_MODE_REG_1_A)
209 li t0,PHYS_TO_K1(A_DUART_MODE_REG_2_
[all...]
H A Dcpu1test.S93 li t0,PHYS_TO_K1(LEDS_PHYS)
151 li s2,PHYS_TO_K1(LEDS_PHYS+LED_CHAR3+1)
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/src/
H A Dbcm91480ht_init.S122 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
126 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
136 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_LO(0x00))
138 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_HI(0x08))
152 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
156 li t0,PHYS_TO_K1(A_GPIO_PIN_SET)
165 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
186 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
205 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(BATTERY_CS))
225 li t0,PHYS_TO_K1(A_BCM1480_IMR_REGISTE
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/board/swarm/src/
H A Dswarm_init.S113 ld t0, PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
153 ld t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
156 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* clear soft reset */
161 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* go unicpu */
216 li t0,PHYS_TO_K1(A_SCD_SYSTEM_CFG)
226 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
230 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
237 li t0,PHYS_TO_K1(A_GPIO_PIN_SET)
241 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
250 li t0,PHYS_TO_K1(A_IO_EXT_CS_BAS
[all...]
H A Ddev_ide.c115 return (*((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr)));
122 return *((volatile uint16_t *) PHYS_TO_K1((reg+disp->baseaddr)));
134 data = *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr));
147 *((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr)) = (uint8_t) (val);
154 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = val;
166 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = data;
/broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/src/
H A Dsentosa_init.S105 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
109 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
116 li t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
125 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
146 li t0,PHYS_TO_K1(A_IMR_REGISTER(0,R_IMR_MAILBOX_CLR_CPU))
154 li t0,PHYS_TO_K1(A_DUART_MODE_REG_1_A)
160 li t0,PHYS_TO_K1(A_DUART_MODE_REG_2_A)
166 li t0,PHYS_TO_K1(A_DUART_CLK_SEL_A)
172 li t0,PHYS_TO_K1(A_DUART_IMR)
179 li t0,PHYS_TO_K1(A_DUART_CMD_
[all...]
H A Dsentosa_devs.c257 reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_STATUS));
309 reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_CMD));
316 reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_DATA));
323 reg = PHYS_TO_K1(A_SMB_REGISTER(chan,R_SMB_START));
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/src/
H A Dcfe_trace.c168 tb_cfg = (volatile uint64_t *) PHYS_TO_K1(A_SCD_TRACE_CFG);
182 at_down_0 = (volatile uint64_t *) PHYS_TO_K1(A_ADDR_TRAP_DOWN_0);
183 at_up_0 = (volatile uint64_t *) PHYS_TO_K1(A_ADDR_TRAP_UP_0);
184 at_cfg_0 = (volatile uint64_t *) PHYS_TO_K1(A_ADDR_TRAP_CFG_0);
186 tb_evt_0 = (volatile uint64_t *) PHYS_TO_K1(A_SCD_TRACE_EVENT_0);
187 tb_evt_4 = (volatile uint64_t *) PHYS_TO_K1(A_SCD_TRACE_EVENT_4);
188 tb_seq_0 = (volatile uint64_t *) PHYS_TO_K1(A_SCD_TRACE_SEQUENCE_0);
189 tb_seq_4 = (volatile uint64_t *) PHYS_TO_K1(A_SCD_TRACE_SEQUENCE_4);
262 tb_cfg = (volatile uint64_t *) PHYS_TO_K1(A_SCD_TRACE_CFG);
274 tb_cfg = (volatile uint64_t *) PHYS_TO_K1(A_SCD_TRACE_CF
[all...]
H A Ddev_sb1250_pcmcia.c123 return *((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr));
128 return *((volatile uint16_t *) PHYS_TO_K1((reg+disp->baseaddr)));
136 data = *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr));
147 *((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr)) = val;
152 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = val;
162 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = data;
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm1250cpci/src/
H A Dbcm1250cpci_init.S111 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
115 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
124 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
145 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
167 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(IDE_CS))
189 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(USBCTL_CS))
210 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(PCMCIA_CS))
232 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(CPCICPLD_CS))
348 1: li t0,PHYS_TO_K1(A_DUART_STATUS_A)
355 li t0,PHYS_TO_K1(A_DUART_TX_HOLD_
[all...]
H A Ddev_ide.c115 return (*((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr)));
122 return *((volatile uint16_t *) PHYS_TO_K1((reg+disp->baseaddr)));
134 data = *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr));
146 *((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr)) = (uint8_t) (val);
153 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = val;
165 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = data;
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/
H A Ddev_ide.c116 return (*((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr)));
123 return *((volatile uint16_t *) PHYS_TO_K1((reg+disp->baseaddr)));
135 data = *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr));
148 *((volatile uint8_t *) PHYS_TO_K1(reg+disp->baseaddr)) = (uint8_t) (val);
155 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = val;
167 *((volatile uint16_t *) PHYS_TO_K1(reg+disp->baseaddr)) = data;
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/
H A Dsb1250_altcpu.S190 la t0,PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
203 la a0,PHYS_TO_K1(A_IMR_REGISTER(0,R_IMR_MAILBOX_CLR_CPU))
206 la a0,PHYS_TO_K1(A_IMR_REGISTER(1,R_IMR_MAILBOX_CLR_CPU))
215 la a0,PHYS_TO_K1(A_SCD_SYSTEM_CFG)
227 1: la a0,PHYS_TO_K1(A_IMR_REGISTER(0,R_IMR_MAILBOX_CPU));
235 la a0,PHYS_TO_K1(A_IMR_REGISTER(0,R_IMR_MAILBOX_CLR_CPU))
270 la t0,PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
285 la t1,PHYS_TO_K1(A_IMR_REGISTER(1,R_IMR_MAILBOX_SET_CPU))
314 la t0,PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
360 li a0,PHYS_TO_K1(A_SCD_SYSTEM_CF
[all...]
H A Dsb1250_l2cache.S97 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
114 # which cannot be expressed with the PHYS_TO_K1 macro,
175 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
190 li t0,PHYS_TO_K1(A_L2_MAKEDISABLE(0x07))
227 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
239 li t0,PHYS_TO_K1(A_L2_MAKEDISABLE(0x0))
277 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
301 li t0,PHYS_TO_K1(A_MC_REGISTER(0,R_MC_CONFIG))
307 li t0,PHYS_TO_K1(A_MC_REGISTER(1,R_MC_CONFIG))
385 li t0,PHYS_TO_K1(A_MC_REGISTE
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/
H A Dbcm1480_altcpu.S92 la reg,PHYS_TO_K1(A_SCD_SYSTEM_CFG) ; \
250 la a0,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_0_CLR_CPU))
265 la a0,PHYS_TO_K1(A_SCD_SYSTEM_CFG)
279 2: la a0,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_0_CPU));
287 la a0,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_0_CLR_CPU))
339 la t1,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_0_SET_CPU))
415 li t2,PHYS_TO_K1(A_SCD_SYSTEM_CFG)
441 la t2,PHYS_TO_K1(A_BCM1480_IMR_REGISTER(0,R_BCM1480_IMR_MAILBOX_0_CLR_CPU))
456 la t2,PHYS_TO_K1(A_SCD_SYSTEM_CFG)
470 2: la t2,PHYS_TO_K1(A_BCM1480_IMR_REGISTE
[all...]
H A Dbcm1480_draminit.c245 #define BCM1480_REFCLK (*((uint64_t *) PHYS_TO_K1(0x1FC00018)))
284 #define PHYS_TO_K1(x) (x) macro
768 sysrev = READCSR(PHYS_TO_K1(A_SCD_SYSTEM_REVISION));
776 plldiv = G_BCM1480_SYS_PLL_DIV(READCSR(PHYS_TO_K1(A_SCD_SYSTEM_CFG)));
1274 base = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx));
1341 drvcfg = READCSR(PHYS_TO_K1(A_BCM1480_MC_BASE(MC_CHAN1))+R_BCM1480_MC_DRIVE_CFG)
1344 WRITECSR(PHYS_TO_K1(A_BCM1480_MC_BASE(MC_CHAN1))+R_BCM1480_MC_DRIVE_CFG,drvcfg);
1380 base = PHYS_TO_K1(A_BCM1480_MC_BASE(mcidx+2));
1423 plldiv = G_BCM1480_SYS_PLL_DIV(READCSR(PHYS_TO_K1(A_SCD_SYSTEM_CFG)));
1461 base = PHYS_TO_K1(A_BCM1480_MC_BAS
[all...]
H A Dbcm1480_l2cache.S95 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
113 # which cannot be expressed with the PHYS_TO_K1 macro,
187 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
203 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_LO(0x0))
205 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_HI(0x8))
244 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
257 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_LO(0xF))
259 li t0,PHYS_TO_K1(A_BCM1480_L2_MAKE_WAY_ENABLE_HI(0xF))
300 li t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
327 la t0, PHYS_TO_K1(A_BCM1480_MC_GLB_CONFI
[all...]
/broadcom-cfe-1.4.2/cfe/arch/mips/board/lausanne/src/
H A Dui_lausanne.c286 *((volatile uint8_t *) PHYS_TO_K1(CPLD_PHYS+0x01)) = (uint8_t) (0x55);
307 data = *((volatile uint8_t *) PHYS_TO_K1(CPLD_PHYS+0xFC));
310 data = *((volatile uint8_t *) PHYS_TO_K1(CPLD_PHYS));
336 *((volatile uint64_t *) PHYS_TO_K1(CPLD_PHYS)) = (uint64_t) (0x8040201008040201ULL);
353 data = *((volatile uint64_t *) PHYS_TO_K1(CPLD_PHYS));
/broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm95836cpci/src/
H A Dbcm95836cpci_init.S97 li a2, PHYS_TO_K1(SB_CHIPC_BASE)
128 li a2, PHYS_TO_K1(BCM95836_CPCI_LED_ADDR)
160 li t0,PHYS_TO_K1(BCM95836_CPCI_LED_ADDR)

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