1/*  *********************************************************************
2    *  SB1250 Board Support Package
3    *
4    *  L2 Cache initialization			File: sb1250_l2cache.S
5    *
6    *  This module contains code to initialize the L2 cache.
7    *
8    *  Note: all the routines in this module rely on registers only,
9    *        since DRAM may not be active yet.
10    *
11    *  Author:  Mitch Lichtenberg
12    *
13    *********************************************************************
14    *
15    *  Copyright 2000,2001,2002,2003
16    *  Broadcom Corporation. All rights reserved.
17    *
18    *  This software is furnished under license and may be used and
19    *  copied only in accordance with the following terms and
20    *  conditions.  Subject to these conditions, you may download,
21    *  copy, install, use, modify and distribute modified or unmodified
22    *  copies of this software in source and/or binary form.  No title
23    *  or ownership is transferred hereby.
24    *
25    *  1) Any source code used, modified or distributed must reproduce
26    *     and retain this copyright notice and list of conditions
27    *     as they appear in the source file.
28    *
29    *  2) No right is granted to use any trade name, trademark, or
30    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
31    *     name may not be used to endorse or promote products derived
32    *     from this software without the prior written permission of
33    *     Broadcom Corporation.
34    *
35    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
36    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
37    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
38    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
39    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
40    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
41    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
43    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
44    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
45    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
46    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
47    *     THE POSSIBILITY OF SUCH DAMAGE.
48    ********************************************************************* */
49
50#include "sbmips.h"
51#include "cpu_config.h"
52#include "mipsmacros.h"
53#include "sb1250_regs.h"
54#include "sb1250_l2c.h"
55#include "sb1250_mc.h"
56#include "sb1250_scd.h"
57
58
59		.text
60		.set mips64
61
62
63/*  *********************************************************************
64    *  Macros
65    ********************************************************************* */
66
67/*#define PHYS_TO_XKPHYS(x) (0x9000000000000000|(x))*/
68#define CACHE_LINE_SIZE	  32
69#ifndef HAZARD
70#define HAZARD ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop
71#endif
72
73
74
75/*  *********************************************************************
76    *  SB1250_L2CACHE_INIT()
77    *
78    *  Initialize the L2 Cache tags to be "invalid"
79    *
80    *  Input parameters:
81    *  	   nothing
82    *
83    *  Return value:
84    *  	   nothing
85    *
86    *  Registers used:
87    *  	   t0,t1,t2
88    ********************************************************************* */
89
90
91LEAF(sb1250_l2cache_init)
92
93_sb1250_l2cache_init:
94
95	# Do nothing (return immediately) if L2 has been disabled via JTAG.
96
97		li	t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
98		ld	t0, 0(t0)
99		and	t0, t0, M_SYS_L2C_RESET
100		beq	zero, t0, 1f
101		jr	ra
1021:
103
104	# Save the old status register, and set the KX bit.
105
106		mfc0	t2,C0_SR
107		or	t1,t2,M_SR_KX
108		mtc0	t1,C0_SR
109		HAZARD
110
111	# Start the index at the base of the cache management
112	# area, but leave the address bit for "Valid" zero.
113	# Note that the management tags are at 00_D000_0000,
114	# which cannot be expressed with the PHYS_TO_K1 macro,
115	# so we will need to use a 64-bit address to get to it.
116
117		dli	t0,PHYS_TO_XKSEG_UNCACHED(A_L2C_MGMT_TAG_BASE)
118
119	# Loop through each entry and each way
120
121#ifdef _FASTINIT_
122		li	t1,16
123#else
124		li	t1,L2C_ENTRIES_PER_WAY*L2C_NUM_WAYS
125#endif
126
127
128	# Write a zero to the cache management register at each
129	# address.
130
131		.align 4
1321:		sd	zero,0(t0)
133		sd	zero,CACHE_LINE_SIZE(t0)
134		sd	zero,2*CACHE_LINE_SIZE(t0)
135		sd	zero,3*CACHE_LINE_SIZE(t0)
136		daddu	t0,(4*CACHE_LINE_SIZE) # size of a cache line
137		subu	t1,4
138		bne	t1,0,1b
139
140	#
141	# Restore old KX bit setting
142	#
143
144		mtc0	t2,C0_SR
145		HAZARD
146
147		j	ra		# return to caller
148
149END(sb1250_l2cache_init)
150
151
152/*  *********************************************************************
153    *  SB1250_L2CACHE_DISABLE()
154    *
155    *  Convert the entire L2 Cache into static memory, for use by
156    *  the bootstrap loader.  Actually, it only removes three of the
157    *  ways, since you must leave at least one way active at all
158    *  times.
159    *
160    *  Input parameters:
161    *  	   nothing
162    *
163    *  Return value:
164    *  	   nothing
165    *
166    *  Registers used:
167    *  	   t0,t1
168    ********************************************************************* */
169
170
171LEAF(sb1250_l2cache_disable)
172
173	# Do nothing (return immediately) if L2 has been disabled via JTAG.
174
175		li	t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
176		ld	t0, 0(t0)
177		and	t0, t0, M_SYS_L2C_RESET
178		beq	zero, t0, 1f
179		jr	ra
1801:
181
182	# Save the old status register, and set the KX bit.
183	# Configure the L2 cache as SRAM (all ways disabled except one)
184	# Do a memory reference at the "way_disable" address
185	# to switch it off.
186	# Warning: do NOT try to configure all of the ways off - you
187	# must leave at least one way active!  This code leaves
188	# way #3 active and gives ways 0..2 to the program.
189
190		li	t0,PHYS_TO_K1(A_L2_MAKEDISABLE(0x07))
191		sd	zero,(t0)
192		ld	t0,(t0)
193
194	# Use the result of the load to stall the pipe here.
195	# Ref sec 5.4.2
196	# XXX is this necessary for global enable/disable operations?
197
198		addu	t0,t0,t0
199
200	# Re-write all the tags
201
202		b	_sb1250_l2cache_init
203
204END(sb1250_l2cache_disable)
205
206
207/*  *********************************************************************
208    *  SB1250_L2CACHE_ENABLE()
209    *
210    *  Convert the L2 Cache memory into the actual L2 cache, enabling
211    *  the cache for future memory accesses.
212    *
213    *  Input parameters:
214    *  	   nothing
215    *
216    *  Return value:
217    *  	   nothing
218    *
219    *  Registers used:
220    *  	   t0,t1
221    ********************************************************************* */
222
223LEAF(sb1250_l2cache_enable)
224
225	# Do nothing (return immediately) if L2 has been disabled via JTAG.
226
227		li	t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
228		ld	t0, 0(t0)
229		and	t0, t0, M_SYS_L2C_RESET
230		beq	zero, t0, 1f
231		jr	ra
2321:
233
234	# Save the old status register, and set the KX bit.
235	# Configure the L2 cache as Cache (all ways enabled)
236	# Do a memory reference at the "way_disable" address
237	# to switch it on.
238
239		li	t0,PHYS_TO_K1(A_L2_MAKEDISABLE(0x0))
240		ld	t0,(t0)
241
242	# Use the result of the load to stall the pipe here.
243	# Ref sec 5.4.2
244	# XXX is this necessary for global enable/disable operations?
245
246		addu	t0,t0,t0
247
248	# Re-write all the tags
249
250		b	_sb1250_l2cache_init
251
252END(sb1250_l2cache_enable)
253
254
255/*  *********************************************************************
256    *  SB1250_L2CACHE_FLUSH()
257    *
258    *  Flush the entire L2 cache.  All dirty lines are written back
259    *  out to memory.
260    *
261    *  Input parameters:
262    *  	   nothing
263    *
264    *  Return value:
265    *  	   nothing
266    *
267    *  Registers used:
268    *      t0, t1, t2, t3: scratch
269    *      t5: saved SR
270    *      t6, t7: saved MC0,1 config values.
271    ********************************************************************* */
272
273LEAF(sb1250_l2cache_flush)
274
275	# Do nothing (return immediately) if L2 has been disabled via JTAG.
276
277		li	t0, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
278		ld	t0, 0(t0)
279		and	t0, t0, M_SYS_L2C_RESET
280		beq	zero, t0, 1f
281		jr	ra
2821:
283
284	# Save the old status register, and set the KX bit.
285
286		mfc0	t5,C0_SR
287		or	t0,t5,M_SR_KX
288		mtc0	t0,C0_SR
289		HAZARD
290
291	#
292	# Set the BERR bits in both memory controllers.  We're
293	# going to do cacheable reads where there is no memory.
294	#
295	#
296	# Note that on an 1125, we can still do this on MC 0 even
297	# though there is only one memory controller.  The register
298	# is there, it just ignores the bits we're trying to write.
299	#
300
301		li	t0,PHYS_TO_K1(A_MC_REGISTER(0,R_MC_CONFIG))
302		ld	t6,0(t0)
303		dli	t1,(M_MC_BERR_DISABLE | M_MC_ECC_DISABLE)
304		or	t1,t1,t6
305		sd	t1,0(t0)
306
307		li	t0,PHYS_TO_K1(A_MC_REGISTER(1,R_MC_CONFIG))
308		ld	t7,0(t0)
309		dli	t1,(M_MC_BERR_DISABLE | M_MC_ECC_DISABLE)
310		or	t1,t1,t7
311		sd	t1,0(t0)
312
313
314	# Flush all of the lines in the cache
315	#
316	# We use the following algorithm, for each way and index of
317	# the cache:
318	#
319	# * do a management mode access to select a victim way.
320	#
321	# * do a cacheable read of an address not in the cache.
322	#
323	# The index used in the second read, in the selected victim way,
324	# will be replaced with the data from the cacheable read.
325	#
326	# We use PAs starting at 30_0000_0000 (in the middle
327	# of the memory expansion area) for the cacheable reads.
328	# They'll return garbage data, but we're just going to
329	# invalidate afterward.
330	#
331	# Note that if the cacheable read is done to an address that
332	# is present in the cache, the victim way will *not* be ejected
333	# (since there's no need to victimize it).
334
335		dli	t0, PHYS_TO_XKPHYS(K_CALG_UNCACHED,
336					   (A_L2C_MGMT_TAG_BASE
337					    | V_L2C_MGMT_ECC_DIAG(1)))
338		dli	t1, PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, 0x3000000000)
339		li	t2, (L2C_ENTRIES_PER_WAY * L2C_NUM_WAYS \
340			     * CACHE_LINE_SIZE)
341
3421:
343		daddiu	t2, -CACHE_LINE_SIZE
344
345		# Select the line to be victimized, and wait for the
346		# read data to return.
347		or	t3, t0, t2
348		ld	t3, 0(t3)
349		daddu	t3, t3, zero
350
351		# Read the high-memory flush address for this line, and
352		# wait for the read data to return.
353		or	t3, t1, t2
354		ld	t3, 0(t3)
355		daddu	t3, t3, zero
356
357		bnez	t2, 1b
358
359
360	#
361	# Now, invalidate the entire cache.  Of course, we could just
362	# reinit the lines we flushed, but this routine is mucking
363	# the entire cache anyway, so it doesn't matter.
364	#
365
366		dli	t0,PHYS_TO_XKSEG_UNCACHED(A_L2C_MGMT_TAG_BASE)
367		li	t1,L2C_ENTRIES_PER_WAY*L2C_NUM_WAYS
368
369	# Write a zero to the cache management register at each
370	# address.
371
3721:		sd	zero,0(t0)
373		sd	zero,CACHE_LINE_SIZE(t0)
374		sd	zero,2*CACHE_LINE_SIZE(t0)
375		sd	zero,3*CACHE_LINE_SIZE(t0)
376		daddu	t0,(4*CACHE_LINE_SIZE) # size of a cache line
377		subu	t1,4
378		bne	t1,0,1b
379
380	#
381	# Restore the old MC register values
382	#
383
384
385		li	t0,PHYS_TO_K1(A_MC_REGISTER(0,R_MC_CONFIG))
386		sd	t6,0(t0)
387
388		li	t0,PHYS_TO_K1(A_MC_REGISTER(1,R_MC_CONFIG))
389		sd	t7,0(t0)
390
391	#
392	# Restore old KX bit setting
393	#
394
395		mtc0	t5,C0_SR
396		HAZARD
397
398		j	ra		# return to caller
399
400END(sb1250_l2cache_flush)
401
402
403
404
405/*  *********************************************************************
406    *  End
407    ********************************************************************* */
408