Searched refs:MC_CHAN1 (Results 1 - 11 of 11) sorted by relevance
| /broadcom-cfe-1.4.2/cfe/arch/mips/board/vcs1280/src/ |
| H A D | vcs1280_init.S | 154 DRAM_CHAN_CFG(MC_CHAN1, DRT10(6,0), DRT10(3,0), MC_64BIT_CHAN, JEDEC, CASCHECK, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
161 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), MC_64BIT_CHAN, JEDEC, CASCHECK, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/src/ |
| H A D | sentosa_init.S | 263 DRAM_CHAN_CFG(MC_CHAN1, DRT10(7,5), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED)
314 DRAM_CHAN_CFG2(MC_CHAN1, DRT10(5,0), DRT10(2,5), FCRAM, CLOSED, BLKSIZE32, NOCSINTLV, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125e/src/ |
| H A D | bcm91125e_init.S | 362 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
390 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125f/src/ |
| H A D | bcm91125f_init.S | 350 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED)
378 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm1250cpci/src/ |
| H A D | bcm1250cpci_init.S | 320 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125pcix/src/ |
| H A D | bcm91125pcix_init.S | 288 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/include/ |
| H A D | sb1250_draminit.h | 277 #define MC_CHAN1 1 macro
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
| H A D | bcm1480_draminit.c | 1341 drvcfg = READCSR(PHYS_TO_K1(A_BCM1480_MC_BASE(MC_CHAN1))+R_BCM1480_MC_DRIVE_CFG)
1344 WRITECSR(PHYS_TO_K1(A_BCM1480_MC_BASE(MC_CHAN1))+R_BCM1480_MC_DRIVE_CFG,drvcfg);
1494 WRITECSR(PHYS_TO_K1(A_BCM1480_MC_BASE(MC_CHAN1))+R_BCM1480_MC_DRIVE_CFG,drvcfg);
3343 if (!(d->mc[MC_CHAN1].csdata[csidx].flags & CS_PRESENT)) continue;
3369 mcbase1 = PHYS_TO_K1(A_BCM1480_MC_BASE(MC_CHAN1));
3667 if ((mcidx == MC_CHAN1) || (mcidx == MC_CHAN3)) break;
3815 if ( (d->mc[mcidx].chantype == MC_64BIT_CHAN) && (mcidx > MC_CHAN1) ) break;
3889 (d->mc[MC_CHAN1].chanintlvint == 1) &&
3905 d->mc[MC_CHAN1].chanintlvint = 0;
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/src/ |
| H A D | bcm91480ht_init.S | 354 DRAM_CHAN_CFG(MC_CHAN1, DRT10(3,0), DRT10(3,0), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK,CSINTLV_2CS , 0, 0 )
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/include/ |
| H A D | bcm1480_draminit.h | 313 #define MC_CHAN1 1 macro
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
| H A D | sb1250_draminit.c | 1380 DRAM_CHAN_CFG(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0),
1405 DRAM_CHAN_CFG(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0),
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Completed in 116 milliseconds