Searched refs:L1C_OP_HITINVAL (Results 1 - 7 of 7) sorted by relevance

/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/
H A Dbcm1480_l1cache.S75 #define L1C_OP_HITINVAL 4 define
255 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(a0)
H A Dbcm1480_cpu.S91 #define L1C_OP_HITINVAL 4 define
282 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(t0)
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/
H A Dsb1250_l1cache.S75 #define L1C_OP_HITINVAL 4 define
263 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(a0)
H A Ddiag_l1cache.h54 #define L1C_OP_HITINVAL 4 macro
H A Dsb1250_cpu.S93 #define L1C_OP_HITINVAL 4 define
301 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(t0)
H A Ddiag_l2cache.S689 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
691 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
693 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
695 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0)
747 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
766 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
1394 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/src/
H A Dbcmcore_l1cache.S73 #define L1C_OP_HITINVAL 4 define
490 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),-LINESIZE(a0)

Completed in 150 milliseconds