Searched refs:L1C_D (Results 1 - 8 of 8) sorted by relevance
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
| H A D | bcm1480_l1cache.S | 81 #define L1C_D 1 define
126 1: cache L1CACHEOP(L1C_D,L1C_OP_IDXSTORETAG),0(t2)
203 1: cache L1CACHEOP(L1C_D,L1C_OP_IDXINVAL),0(t2)
230 1: cache L1CACHEOP(L1C_D,L1C_OP_HITWRITEBACK),0(a0)
255 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(a0)
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| H A D | bcm1480_cpu.S | 97 #define L1C_D 1 define
282 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(t0)
296 1: cache L1CACHEOP(L1C_D,L1C_OP_HITWRITEBACK),0(t0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
| H A D | sb1250_l1cache.S | 81 #define L1C_D 1 define
134 1: cache L1CACHEOP(L1C_D,L1C_OP_IDXSTORETAG),0(t2)
211 1: cache L1CACHEOP(L1C_D,L1C_OP_IDXINVAL),0(t2)
238 1: cache L1CACHEOP(L1C_D,L1C_OP_HITWRITEBACK),0(a0)
263 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(a0)
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| H A D | sb1250_cpu.S | 99 #define L1C_D 1 define
301 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(t0)
315 1: cache L1CACHEOP(L1C_D,L1C_OP_HITWRITEBACK),0(t0)
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| H A D | diag_l1cache.h | 61 #define L1C_D 1 macro
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| H A D | diag_l2cache.S | 666 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \
676 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \
689 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
691 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
693 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
695 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0)
747 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
766 cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
1333 cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \
1339 /*cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVA
[all...] |
| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/src/ |
| H A D | bcmcore_l1cache.S | 80 #define L1C_D 1 define
446 cache L1CACHEOP(L1C_D,L1C_OP_HITWBINVAL),-LINESIZE(a0)
490 1: cache L1CACHEOP(L1C_D,L1C_OP_HITINVAL),-LINESIZE(a0)
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| H A D | bcmcore_cpuinit.S | 81 #define L1C_D 1 define
376 1: cache CACHEOP(L1C_D,CACHE_OP_HITINVAL),0(t0)
392 cache CACHEOP(L1C_D,CACHE_OP_HITWRITEBACK_INVAL),0(t0)
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