| /broadcom-cfe-1.4.2/cfe/arch/mips/board/vcs1280/src/ |
| H A D | vcs1280_init.S | 148 DRAM_CHAN_CFG(MC_CHAN0, DRT10(6,0), DRT10(3,0), MC_64BIT_CHAN, JEDEC, CASCHECK, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
154 DRAM_CHAN_CFG(MC_CHAN1, DRT10(6,0), DRT10(3,0), MC_64BIT_CHAN, JEDEC, CASCHECK, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
161 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), MC_64BIT_CHAN, JEDEC, CASCHECK, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91480ht/src/ |
| H A D | bcm91480ht_init.S | 338 * DRAM_CHAN_CFG(chan,tMEMCLK,tROUNDTRIP,chantype,dramtype,pagepolicy,csintlv,ecc,flg)
350 DRAM_CHAN_CFG(MC_CHAN0, DRT10(3,0), DRT10(3,0), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK,CSINTLV_2CS ,0 , 0 )
354 DRAM_CHAN_CFG(MC_CHAN1, DRT10(3,0), DRT10(3,0), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK,CSINTLV_2CS , 0, 0 )
377 DRAM_CHAN_CFG(MC_CHAN2, DRT10(3,0), DRT10(3,5), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK, 0, 0, MCFLG_2T | MCFLG_NO_ODT_CS)
384 DRAM_CHAN_CFG(MC_CHAN3, DRT10(3,0), DRT10(3,5), MC_32BIT_CHAN, DRAM_TYPE_SPD, CASCHECK, 0, 0, MCFLG_2T | MCFLG_NO_ODT_CS)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm1250cpci/src/ |
| H A D | bcm1250cpci_init.S | 302 DRAM_CHAN_CFG(MC_CHAN0, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
320 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/sentosa/src/ |
| H A D | sentosa_init.S | 243 DRAM_CHAN_CFG(MC_CHAN0, DRT10(7,5), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED)
263 DRAM_CHAN_CFG(MC_CHAN1, DRT10(7,5), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/include/ |
| H A D | sb1250_draminit.h | 89 #define DRAM_CHAN_CFG(chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \ macro
112 #define DRAM_CHAN_CFG(chan,tMEMCLK,dramtype,pagepolicy,blksize,csintlv,ecc,flg) \ macro
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125e/src/ |
| H A D | bcm91125e_init.S | 362 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
390 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125f/src/ |
| H A D | bcm91125f_init.S | 350 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED)
378 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, MCFLG_DS_REDUCED)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/include/ |
| H A D | bcm1480_draminit.h | 86 #define DRAM_CHAN_CFG(chan,tMEMCLK,tROUNDTRIP,chantype,dramtype,pagepolicy,csintlv,ecc,flg) \ macro
117 #define DRAM_CHAN_CFG(chan,tMEMCLK,tROUNDTRIP,chantype,dramtype,pagepolicy,csintlv,ecc,flg) \ macro
311 /* Channels. DRAM_CHAN_CFG */
317 /* Channel type. DRAM_CHAN_CFG */
321 /* DRAM type. DRAM_CHAN_CFG */
328 /* Page policy. DRAM_CHAN_CFG */
332 /* Chip Select interleaving options. DRAM_CHAN_CFG */
338 /* ECC enable. DRAM_CHAN_CFG */
343 /* Flags for channel configuration. DRAM_CHAN_CFG */
344 #define MCFLG_ECC_ENABLE 0x01 /* Used to compare ECC field in DRAM_CHAN_CFG */
[all...] |
| /broadcom-cfe-1.4.2/cfe/arch/mips/board/bcm91125pcix/src/ |
| H A D | bcm91125pcix_init.S | 288 DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
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| /broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
| H A D | sb1250_draminit.c | 1323 DRAM_CHAN_CFG(MC_CHAN0, 80, JEDEC, CASCHECK, BLKSIZE32, NOCSINTLV, ECCDISABLE, 0),
1344 DRAM_CHAN_CFG(MC_CHAN0, 80, JEDEC, CASCHECK, BLKSIZE32, NOCSINTLV, ECCDISABLE, 0),
1371 DRAM_CHAN_CFG(MC_CHAN0, CFG_DRAM_MIN_tMEMCLK, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0),
1380 DRAM_CHAN_CFG(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0),
1405 DRAM_CHAN_CFG(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0),
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