Searched refs:ADD (Results 51 - 75 of 91) sorted by relevance

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/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/
H A DMips16ISelDAGToDAG.cpp200 // Operand is a result from an ADD.
201 if (Addr.getOpcode() == ISD::ADD) {
256 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
H A DMipsSEISelDAGToDAG.cpp223 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
279 // Operand is a result from an ADD.
280 if (Addr.getOpcode() == ISD::ADD) {
/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp97 if (Addr.getOpcode() == ISD::ADD) {
/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp97 case ISD::ADD:
553 case ISD::ADD:
782 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
824 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1257 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1437 case ISD::ADD:
2559 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2680 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2737 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2756 BasePtr = DAG.getNode(ISD::ADD, d
[all...]
H A DTargetLowering.cpp968 case ISD::ADD:
1217 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1641 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1667 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1729 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1838 if (N->getOpcode() == ISD::ADD) {
1951 if (Op.getOpcode() == ISD::ADD) {
2498 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2521 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2587 NPQ = DAG.getNode(ISD::ADD, d
[all...]
H A DSelectionDAGBuilder.h474 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
H A DSelectionDAGDumper.cpp155 case ISD::ADD: return "add";
H A DSelectionDAG.cpp2025 case ISD::ADD:
2039 if (Op.getOpcode() == ISD::ADD) {
2231 case ISD::ADD:
2237 // Special case decrementing a value (ADD X, -1):
2342 /// ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an
2344 /// semantics as an ADD. This handles the equivalence:
2347 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
2729 case ISD::ADD:
2839 case ISD::ADD:
3198 case ISD::ADD
[all...]
H A DSelectionDAGBuilder.cpp1212 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3145 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3168 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3197 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3236 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3314 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3378 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3787 DAG.getNode(ISD::ADD, dl, MVT::i32,
4161 DAG.getNode(ISD::ADD, dl, MVT::i32,
4269 DAG.getNode(ISD::ADD, d
[all...]
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp849 setTargetDAGCombine(ISD::ADD);
1322 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1496 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1514 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1517 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
2326 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2367 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2728 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
3174 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
3296 SDValue Addr = DAG.getNode(ISD::ADD, d
[all...]
H A DARMISelDAGToDAG.cpp344 if (N->getOpcode() != ISD::ADD)
531 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
601 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
602 // ISD::OR that is equivalent to an ISD::ADD.
607 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
700 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
701 // ISD::OR that is equivalent to an ADD.
1057 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1265 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1316 if (N.getOpcode() != ISD::ADD
[all...]
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp483 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
604 if (Ptr->getOpcode() != ISD::ADD)
608 isInc = (Ptr->getOpcode() == ISD::ADD);
755 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
978 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1527 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
H A DHexagonISelDAGToDAG.cpp1350 case ISD::ADD:
1508 if (Addr.getOpcode() != ISD::ADD) {
1539 if (Addr.getOpcode() == ISD::ADD) {
1568 if (Addr.getOpcode() == ISD::ADD) {
1650 if (N.getOpcode() == ISD::ADD) {
/freebsd-10.0-release/contrib/byacc/test/
H A Dquote_calc.tab.c146 #define ADD 258 macro
265 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
H A Dquote_calc2.tab.c146 #define ADD 258 macro
265 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
276 "expr : expr \"ADD\" expr",
/freebsd-10.0-release/contrib/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp42 setOperationAction(ISD::ADD, MVT::v4i32, Expand);
777 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
861 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
910 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
H A DSIISelLowering.cpp67 setOperationAction(ISD::ADD, MVT::i64, Legal);
68 setOperationAction(ISD::ADD, MVT::i32, Legal);
/freebsd-10.0-release/contrib/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp310 case X86ISD::ADD:
315 case ISD::ADD:
1100 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1185 case ISD::ADD: {
1421 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1514 ADD, enumerator in enum:AtomicOpc
1649 if (Op == ADD) {
1650 // Translate to INC/DEC if ADD by 1 or -1.
1656 // Translate to SUB if ADD by negative value.
1666 if (Op == ADD
[all...]
H A DX86ISelLowering.h274 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
275 ADD, SUB, ADC, SBB, SMUL, enumerator in enum:llvm::X86ISD::NodeType
/freebsd-10.0-release/sbin/setkey/
H A Dparse.y96 %token ADD GET DELETE DELETEALL FLUSH DUMP
152 : ADD ipaddropts ipaddr ipaddr protocol_spec spi extension_spec algorithm_spec EOT
/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp545 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
660 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1049 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1091 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1189 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1234 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
1419 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
H A DSystemZISelDAGToDAG.cpp319 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp516 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
939 DAG.getNode(ISD::ADD, dl, getPointerTy(),
1000 if (Op->getOpcode() != ISD::ADD)
/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp536 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[i],
578 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[i],
1118 SDValue Addr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
1210 DAG.getNode(ISD::ADD, dl, getPointerTy(), localcopy,
/freebsd-10.0-release/sys/dev/an/
H A Dif_an.c793 #define ADD(s, o) ifmedia_add(&sc->an_ifmedia, \ macro
795 ADD(IFM_AUTO, 0);
796 ADD(IFM_AUTO, IFM_IEEE80211_ADHOC);
804 ADD(mword, 0);
805 ADD(mword, IFM_IEEE80211_ADHOC);
810 #undef ADD macro

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