/freebsd-10.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 200 // Operand is a result from an ADD. 201 if (Addr.getOpcode() == ISD::ADD) { 256 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
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H A D | MipsSEISelDAGToDAG.cpp | 223 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); 279 // Operand is a result from an ADD. 280 if (Addr.getOpcode() == ISD::ADD) {
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/freebsd-10.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelDAGToDAG.cpp | 97 if (Addr.getOpcode() == ISD::ADD) {
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorTypes.cpp | 97 case ISD::ADD: 553 case ISD::ADD: 782 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 824 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1257 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 1437 case ISD::ADD: 2559 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2680 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), 2737 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 2756 BasePtr = DAG.getNode(ISD::ADD, d [all...] |
H A D | TargetLowering.cpp | 968 case ISD::ADD: 1217 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1641 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 1667 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 1729 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 1838 if (N->getOpcode() == ISD::ADD) { 1951 if (Op.getOpcode() == ISD::ADD) { 2498 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2521 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2587 NPQ = DAG.getNode(ISD::ADD, d [all...] |
H A D | SelectionDAGBuilder.h | 474 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
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H A D | SelectionDAGDumper.cpp | 155 case ISD::ADD: return "add";
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H A D | SelectionDAG.cpp | 2025 case ISD::ADD: 2039 if (Op.getOpcode() == ISD::ADD) { 2231 case ISD::ADD: 2237 // Special case decrementing a value (ADD X, -1): 2342 /// ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an 2344 /// semantics as an ADD. This handles the equivalence: 2347 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) || 2729 case ISD::ADD: 2839 case ISD::ADD: 3198 case ISD::ADD [all...] |
H A D | SelectionDAGBuilder.cpp | 1212 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3145 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3168 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3197 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3236 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3314 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3378 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3787 DAG.getNode(ISD::ADD, dl, MVT::i32, 4161 DAG.getNode(ISD::ADD, dl, MVT::i32, 4269 DAG.getNode(ISD::ADD, d [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 849 setTargetDAGCombine(ISD::ADD); 1322 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1496 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1514 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1517 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 2326 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2367 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2728 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 3174 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 3296 SDValue Addr = DAG.getNode(ISD::ADD, d [all...] |
H A D | ARMISelDAGToDAG.cpp | 344 if (N->getOpcode() != ISD::ADD) 531 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 601 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 602 // ISD::OR that is equivalent to an ISD::ADD. 607 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) { 700 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 701 // ISD::OR that is equivalent to an ADD. 1057 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) { 1265 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 1316 if (N.getOpcode() != ISD::ADD [all...] |
/freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 483 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 604 if (Ptr->getOpcode() != ISD::ADD) 608 isInc = (Ptr->getOpcode() == ISD::ADD); 755 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase, 978 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 1527 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(),
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H A D | HexagonISelDAGToDAG.cpp | 1350 case ISD::ADD: 1508 if (Addr.getOpcode() != ISD::ADD) { 1539 if (Addr.getOpcode() == ISD::ADD) { 1568 if (Addr.getOpcode() == ISD::ADD) { 1650 if (N.getOpcode() == ISD::ADD) {
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/freebsd-10.0-release/contrib/byacc/test/ |
H A D | quote_calc.tab.c | 146 #define ADD 258 macro 265 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
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H A D | quote_calc2.tab.c | 146 #define ADD 258 macro 265 0,0,0,0,0,0,"OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV", 276 "expr : expr \"ADD\" expr",
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/freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 42 setOperationAction(ISD::ADD, MVT::v4i32, Expand); 777 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr, 861 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, 910 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
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H A D | SIISelLowering.cpp | 67 setOperationAction(ISD::ADD, MVT::i64, Legal); 68 setOperationAction(ISD::ADD, MVT::i32, Legal);
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/freebsd-10.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 310 case X86ISD::ADD: 315 case ISD::ADD: 1100 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && 1185 case ISD::ADD: { 1421 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA 1514 ADD, enumerator in enum:AtomicOpc 1649 if (Op == ADD) { 1650 // Translate to INC/DEC if ADD by 1 or -1. 1656 // Translate to SUB if ADD by negative value. 1666 if (Op == ADD [all...] |
H A D | X86ISelLowering.h | 274 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. 275 ADD, SUB, ADC, SBB, SMUL, enumerator in enum:llvm::X86ISD::NodeType
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/freebsd-10.0-release/sbin/setkey/ |
H A D | parse.y | 96 %token ADD GET DELETE DELETEALL FLUSH DUMP 152 : ADD ipaddropts ipaddr ipaddr protocol_spec spi extension_spec algorithm_spec EOT
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/freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 545 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4)); 660 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, 1049 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result, 1091 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset); 1189 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr, 1234 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust); 1419 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
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H A D | SystemZISelDAGToDAG.cpp | 319 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
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/freebsd-10.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 516 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 939 DAG.getNode(ISD::ADD, dl, getPointerTy(), 1000 if (Op->getOpcode() != ISD::ADD)
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/freebsd-10.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 536 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[i], 578 DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[i], 1118 SDValue Addr = DAG.getNode(ISD::ADD, dl, getPointerTy(), 1210 DAG.getNode(ISD::ADD, dl, getPointerTy(), localcopy,
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/freebsd-10.0-release/sys/dev/an/ |
H A D | if_an.c | 793 #define ADD(s, o) ifmedia_add(&sc->an_ifmedia, \ macro 795 ADD(IFM_AUTO, 0); 796 ADD(IFM_AUTO, IFM_IEEE80211_ADHOC); 804 ADD(mword, 0); 805 ADD(mword, IFM_IEEE80211_ADHOC); 810 #undef ADD macro
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