accelerants/radeon/set_mode.h

13 // PLL divider values
115 	// Bios values used by Mobility Asics
209 	display_mode *mode, crtc_regs *values );
211 	crtc_regs *values );
216 void Radeon_CalcPLLRegisters( const display_mode *mode, const pll_dividers *dividers, pll_regs *values );
217 void Radeon_ProgramPLL( accelerator_info *ai, int crtc_idx, pll_regs *values );
233 void Radeon_ReadRMXRegisters( accelerator_info *ai, fp_regs *values );
234 void Radeon_CalcRMXRegisters( fp_info *flatpanel, display_mode *mode, bool use_rmx, fp_regs *values );
235 void Radeon_ProgramRMXRegisters( accelerator_info *ai, fp_regs *values );
237 void Radeon_ReadFPRegisters( accelerator_info *ai, fp_regs *values );
239 	fp_info *fp_port, crtc_regs *crtc_values, fp_regs *values );
241 	fp_info *fp_port, fp_regs *values );
246 	accelerator_info *ai, routing_regs *values );
248 	accelerator_info *ai, const impactv_params *tv_parameters, routing_regs *values );
250 	accelerator_info *ai, routing_regs *values );
268 	impactv_params *params, impactv_regs *values, int crtc_idx,
271 	accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values, bool internal_encoder );
273 	accelerator_info *ai, impactv_write_FIFO write, impactv_regs *values );
277 void Radeon_TheatreProgramTVRegisters( accelerator_info *ai, impactv_regs *values );
278 void Radeon_TheatreReadTVRegisters( accelerator_info *ai, impactv_regs *values );
283 void Radeon_InternalTVOutProgramRegisters( accelerator_info *ai, impactv_regs *values );
284 void Radeon_InternalTVOutReadRegisters( accelerator_info *ai, impactv_regs *values );