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46fa23f9 |
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08-May-2022 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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d39088ad |
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08-May-2022 |
Samuel Holland <samuel@sholland.org> |
reset: sunxi: Get the reset count from the CCU descriptor This allows all of the clock drivers to use a common bind function. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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49b2b0a2 |
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08-May-2022 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi: Store the array sizes in the CCU descriptor The reset array size is currently used for bounds checking in the reset driver. The same bounds check should really be done in the clock driver. Currently, the array size is provided to the reset driver separately from the CCU descriptor, which is a bit strange. Let's do this the usual way, with the array sizes next to the arrays themselves. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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d6cb09d8 |
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04-May-2022 |
Andre Przywara <andre.przywara@arm.com> |
clk: sunxi: add and use dummy gate clocks Some devices enumerate various clocks in their DT, and many drivers just blanketly try to enable all of them. This creates problems since we only model a few gate clocks, and the clock driver outputs a warning when a clock is not described: ========= sunxi_set_gate: (CLK#3) unhandled ========= Some clocks don't have an enable bit, or are already enabled in a different way, so we might want to just ignore them. Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define a GATE_DUMMY macro that can be used in the clock description array. Define a few clocks, used by some pinctrl devices, that way to suppress the runtime warnings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> |
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596247e5 |
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23-Apr-2022 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi: h6_r: Correct the driver name H6 is from the sun50i family, not sun6i. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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23c83366 |
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12-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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d6cb09d8 |
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04-May-2022 |
Andre Przywara <andre.przywara@arm.com> |
clk: sunxi: add and use dummy gate clocks Some devices enumerate various clocks in their DT, and many drivers just blanketly try to enable all of them. This creates problems since we only model a few gate clocks, and the clock driver outputs a warning when a clock is not described: ========= sunxi_set_gate: (CLK#3) unhandled ========= Some clocks don't have an enable bit, or are already enabled in a different way, so we might want to just ignore them. Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define a GATE_DUMMY macro that can be used in the clock description array. Define a few clocks, used by some pinctrl devices, that way to suppress the runtime warnings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> |
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596247e5 |
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23-Apr-2022 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi: h6_r: Correct the driver name H6 is from the sun50i family, not sun6i. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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23c83366 |
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12-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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23c83366 |
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12-Sep-2021 |
Samuel Holland <samuel@sholland.org> |
clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |