#
2f9886c6 |
|
27-Oct-2023 |
Patrice Chotard <patrice.chotard@foss.st.com> |
arm: caches: Make DCACHE_DEFAULT_OPTION accessible for ARM64 arch This fixes the following compilation error in ARM64: arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’: arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function) 59 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); | ^~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
31565bb0 |
|
29-Aug-2023 |
Andre Przywara <andre.przywara@arm.com> |
driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registers The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS system registers, that provide 64 bits worth of randomness on every read. Since it's an extension, and implementing it is optional, there is a field in the ID_AA64ISAR0_EL1 ID register to query the availability of those registers. Add a UCLASS_RNG driver that returns entropy via repeated reads from those system registers, if the extension is implemented. The driver always binds, but checks the availability in the probe() routine. This helps systems which suffer from low boot entropy, since U-Boot can provide entropy via the generic UEFI entropy gathering protocol to the OS, at an early stage. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6c7691ed |
|
11-Feb-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: Always unmask SErrors The ARMv8 architecture describes the "SError interrupt" as the fourth kind of exception, next to synchronous exceptions, IRQs, and FIQs. Those SErrors signal exceptional conditions from which the system might not easily recover, and are normally generated by the interconnect as a response to some bus error. A typical situation is access to a non-existing memory address or device, but it might be deliberately triggered by a device as well. The SError interrupt replaces the Armv7 asynchronous abort. Trusted Firmware enters U-Boot (BL33) typically with SErrors masked, and we never enable them. However any SError condition still triggers the SError interrupt, and this condition stays pending, it just won't be handled. If now later on the Linux kernel unmasks the "A" bit in PState, it will immediately take the exception, leading to a kernel crash. This leaves many people scratching their head about the reason for this, and leads to long debug sessions, possibly looking at the wrong places (the kernel, but not U-Boot). To avoid the situation, just unmask SErrors early in the ARMv8 boot process, so that the U-Boot exception handlers reports them in a timely manner. As SErrors are typically asynchronous, the register dump does not need to point at the actual culprit, but it should happen very shortly after the condition. For those exceptions to be taken, we also need to route them to EL2, if U-Boot is running in this exception level. This removes the respective code snippet from the Freescale lowlevel routine, as this is now handled in generic ARMv8 code. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
00179319 |
|
03-Sep-2021 |
Tom Rini <trini@konsulko.com> |
Revert most of the series for adding vexpress_aemv8r support Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits: e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs 30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1 b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant 2f5b7b74903f armv8: Add ARMv8 MPU configuration logic 37a757e227cc armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7befc849 |
|
23-Aug-2021 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
psci: fix double declaration The prototype of psci_features() duplicated. Remove extra declaration. Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1") Reported-by: Michael Scott <mike@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
#
37a757e2 |
|
19-Aug-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Ensure EL1&0 VMSA is enabled On Armv8-R, the EL1&0 memory system architecture is configurable as a VMSA or PMSA, and resets to an "architecturally unknown" value. Add code to armv8_switch_to_el1_m which detects whether the MSA at EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields. If it is we must ensure the VMSA is enabled so that a rich OS can boot. The MSA and MSA_FRAC fields are described in the Armv8-R architecture profile supplement (section G1.3.7): https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
53b40e8d |
|
19-Aug-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Disable pointer authentication traps for EL1 The use of ARMv8.3 pointer authentication (PAuth) is governed by fields in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset value of these fields is 'architecturally unknown' so we must ensure that the fields are enabled (to disable the traps) if we are entering the kernel at EL1. The APK field disables PAuth instruction traps and the API field disables PAuth register traps Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer authentication is supported by the hardware. The runtime checks require a second temporary register, so add this to the EL1 transition macro signature and update 2 call sites. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
c48fec6e |
|
12-Jul-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Initialize CNTFRQ if at highest exception level CNTFRQ_EL0 is only writable from the highest supported exception level on the platform. For Armv8-A, this is typically EL3, but technically EL2 and EL3 are optional so it may need to be initialized at EL2 or EL1. For Armv8-R, the highest exception level is always EL2. This patch moves the initialization outside of the switch_el block and uses a new macro branch_if_not_highest_el which dynamically detects whether it is at the highest supported exception level. Linux's docs state that CNTFRQ_EL0 should be initialized by the bootloader. If not set, the the U-Boot prompt countdown hangs. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
2740edaf |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove set_dacr/get_dacr functions Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel <ardb@kernel.org> Serie-cc: R Sricharan <r.sricharan@ti.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
9b39d249 |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: cosmetic: align TTB_SECT define value Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
342e1abd |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
42d0d422 |
|
28-Nov-2020 |
Ovidiu Panait <ovidiu.panait@windriver.com> |
common: board_r: Drop initr_noncached wrapper Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6744ace5 |
|
06-Jul-2020 |
Ard Biesheuvel <ardb@kernel.org> |
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
31565bb0 |
|
29-Aug-2023 |
Andre Przywara <andre.przywara@arm.com> |
driver: rng: Add DM_RNG interface for ARMv8.5 RNDR registers The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS system registers, that provide 64 bits worth of randomness on every read. Since it's an extension, and implementing it is optional, there is a field in the ID_AA64ISAR0_EL1 ID register to query the availability of those registers. Add a UCLASS_RNG driver that returns entropy via repeated reads from those system registers, if the extension is implemented. The driver always binds, but checks the availability in the probe() routine. This helps systems which suffer from low boot entropy, since U-Boot can provide entropy via the generic UEFI entropy gathering protocol to the OS, at an early stage. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6c7691ed |
|
11-Feb-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: Always unmask SErrors The ARMv8 architecture describes the "SError interrupt" as the fourth kind of exception, next to synchronous exceptions, IRQs, and FIQs. Those SErrors signal exceptional conditions from which the system might not easily recover, and are normally generated by the interconnect as a response to some bus error. A typical situation is access to a non-existing memory address or device, but it might be deliberately triggered by a device as well. The SError interrupt replaces the Armv7 asynchronous abort. Trusted Firmware enters U-Boot (BL33) typically with SErrors masked, and we never enable them. However any SError condition still triggers the SError interrupt, and this condition stays pending, it just won't be handled. If now later on the Linux kernel unmasks the "A" bit in PState, it will immediately take the exception, leading to a kernel crash. This leaves many people scratching their head about the reason for this, and leads to long debug sessions, possibly looking at the wrong places (the kernel, but not U-Boot). To avoid the situation, just unmask SErrors early in the ARMv8 boot process, so that the U-Boot exception handlers reports them in a timely manner. As SErrors are typically asynchronous, the register dump does not need to point at the actual culprit, but it should happen very shortly after the condition. For those exceptions to be taken, we also need to route them to EL2, if U-Boot is running in this exception level. This removes the respective code snippet from the Freescale lowlevel routine, as this is now handled in generic ARMv8 code. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
00179319 |
|
03-Sep-2021 |
Tom Rini <trini@konsulko.com> |
Revert most of the series for adding vexpress_aemv8r support Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits: e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs 30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1 b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant 2f5b7b74903f armv8: Add ARMv8 MPU configuration logic 37a757e227cc armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7befc849 |
|
23-Aug-2021 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
psci: fix double declaration The prototype of psci_features() duplicated. Remove extra declaration. Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1") Reported-by: Michael Scott <mike@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
#
37a757e2 |
|
19-Aug-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Ensure EL1&0 VMSA is enabled On Armv8-R, the EL1&0 memory system architecture is configurable as a VMSA or PMSA, and resets to an "architecturally unknown" value. Add code to armv8_switch_to_el1_m which detects whether the MSA at EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields. If it is we must ensure the VMSA is enabled so that a rich OS can boot. The MSA and MSA_FRAC fields are described in the Armv8-R architecture profile supplement (section G1.3.7): https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
53b40e8d |
|
19-Aug-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Disable pointer authentication traps for EL1 The use of ARMv8.3 pointer authentication (PAuth) is governed by fields in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset value of these fields is 'architecturally unknown' so we must ensure that the fields are enabled (to disable the traps) if we are entering the kernel at EL1. The APK field disables PAuth instruction traps and the API field disables PAuth register traps Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer authentication is supported by the hardware. The runtime checks require a second temporary register, so add this to the EL1 transition macro signature and update 2 call sites. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
c48fec6e |
|
12-Jul-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Initialize CNTFRQ if at highest exception level CNTFRQ_EL0 is only writable from the highest supported exception level on the platform. For Armv8-A, this is typically EL3, but technically EL2 and EL3 are optional so it may need to be initialized at EL2 or EL1. For Armv8-R, the highest exception level is always EL2. This patch moves the initialization outside of the switch_el block and uses a new macro branch_if_not_highest_el which dynamically detects whether it is at the highest supported exception level. Linux's docs state that CNTFRQ_EL0 should be initialized by the bootloader. If not set, the the U-Boot prompt countdown hangs. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
2740edaf |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove set_dacr/get_dacr functions Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel <ardb@kernel.org> Serie-cc: R Sricharan <r.sricharan@ti.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
9b39d249 |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: cosmetic: align TTB_SECT define value Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
342e1abd |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
42d0d422 |
|
28-Nov-2020 |
Ovidiu Panait <ovidiu.panait@windriver.com> |
common: board_r: Drop initr_noncached wrapper Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6744ace5 |
|
06-Jul-2020 |
Ard Biesheuvel <ardb@kernel.org> |
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <masahiroy@kernel.org> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
6c7691ed |
|
11-Feb-2022 |
Andre Przywara <andre.przywara@arm.com> |
armv8: Always unmask SErrors The ARMv8 architecture describes the "SError interrupt" as the fourth kind of exception, next to synchronous exceptions, IRQs, and FIQs. Those SErrors signal exceptional conditions from which the system might not easily recover, and are normally generated by the interconnect as a response to some bus error. A typical situation is access to a non-existing memory address or device, but it might be deliberately triggered by a device as well. The SError interrupt replaces the Armv7 asynchronous abort. Trusted Firmware enters U-Boot (BL33) typically with SErrors masked, and we never enable them. However any SError condition still triggers the SError interrupt, and this condition stays pending, it just won't be handled. If now later on the Linux kernel unmasks the "A" bit in PState, it will immediately take the exception, leading to a kernel crash. This leaves many people scratching their head about the reason for this, and leads to long debug sessions, possibly looking at the wrong places (the kernel, but not U-Boot). To avoid the situation, just unmask SErrors early in the ARMv8 boot process, so that the U-Boot exception handlers reports them in a timely manner. As SErrors are typically asynchronous, the register dump does not need to point at the actual culprit, but it should happen very shortly after the condition. For those exceptions to be taken, we also need to route them to EL2, if U-Boot is running in this exception level. This removes the respective code snippet from the Freescale lowlevel routine, as this is now handled in generic ARMv8 code. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
00179319 |
|
03-Sep-2021 |
Tom Rini <trini@konsulko.com> |
Revert most of the series for adding vexpress_aemv8r support Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits: e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs 30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1 b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant 2f5b7b74903f armv8: Add ARMv8 MPU configuration logic 37a757e227cc armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7befc849 |
|
23-Aug-2021 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
psci: fix double declaration The prototype of psci_features() duplicated. Remove extra declaration. Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1") Reported-by: Michael Scott <mike@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
#
37a757e2 |
|
19-Aug-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Ensure EL1&0 VMSA is enabled On Armv8-R, the EL1&0 memory system architecture is configurable as a VMSA or PMSA, and resets to an "architecturally unknown" value. Add code to armv8_switch_to_el1_m which detects whether the MSA at EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields. If it is we must ensure the VMSA is enabled so that a rich OS can boot. The MSA and MSA_FRAC fields are described in the Armv8-R architecture profile supplement (section G1.3.7): https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
53b40e8d |
|
19-Aug-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Disable pointer authentication traps for EL1 The use of ARMv8.3 pointer authentication (PAuth) is governed by fields in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset value of these fields is 'architecturally unknown' so we must ensure that the fields are enabled (to disable the traps) if we are entering the kernel at EL1. The APK field disables PAuth instruction traps and the API field disables PAuth register traps Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer authentication is supported by the hardware. The runtime checks require a second temporary register, so add this to the EL1 transition macro signature and update 2 call sites. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
c48fec6e |
|
12-Jul-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Initialize CNTFRQ if at highest exception level CNTFRQ_EL0 is only writable from the highest supported exception level on the platform. For Armv8-A, this is typically EL3, but technically EL2 and EL3 are optional so it may need to be initialized at EL2 or EL1. For Armv8-R, the highest exception level is always EL2. This patch moves the initialization outside of the switch_el block and uses a new macro branch_if_not_highest_el which dynamically detects whether it is at the highest supported exception level. Linux's docs state that CNTFRQ_EL0 should be initialized by the bootloader. If not set, the the U-Boot prompt countdown hangs. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
2740edaf |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove set_dacr/get_dacr functions Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel <ardb@kernel.org> Serie-cc: R Sricharan <r.sricharan@ti.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
9b39d249 |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: cosmetic: align TTB_SECT define value Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
342e1abd |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
42d0d422 |
|
28-Nov-2020 |
Ovidiu Panait <ovidiu.panait@windriver.com> |
common: board_r: Drop initr_noncached wrapper Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6744ace5 |
|
06-Jul-2020 |
Ard Biesheuvel <ardb@kernel.org> |
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
00179319 |
|
03-Sep-2021 |
Tom Rini <trini@konsulko.com> |
Revert most of the series for adding vexpress_aemv8r support Per a request from Andre Przywara and agreed with by Peter Hoyes, the vexpress aemv8r support wasn't quite ready to be merged, but the discussion had moved off list. We should keep the first patch in the series for now, but revert the rest. This reverts the following commits: e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs 30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1 b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant 2f5b7b74903f armv8: Add ARMv8 MPU configuration logic 37a757e227cc armv8: Ensure EL1&0 VMSA is enabled Signed-off-by: Tom Rini <trini@konsulko.com> |
#
7befc849 |
|
23-Aug-2021 |
Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
psci: fix double declaration The prototype of psci_features() duplicated. Remove extra declaration. Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1") Reported-by: Michael Scott <mike@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> |
#
37a757e2 |
|
19-Aug-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Ensure EL1&0 VMSA is enabled On Armv8-R, the EL1&0 memory system architecture is configurable as a VMSA or PMSA, and resets to an "architecturally unknown" value. Add code to armv8_switch_to_el1_m which detects whether the MSA at EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields. If it is we must ensure the VMSA is enabled so that a rich OS can boot. The MSA and MSA_FRAC fields are described in the Armv8-R architecture profile supplement (section G1.3.7): https://developer.arm.com/documentation/ddi0600/latest/ Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
53b40e8d |
|
19-Aug-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Disable pointer authentication traps for EL1 The use of ARMv8.3 pointer authentication (PAuth) is governed by fields in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset value of these fields is 'architecturally unknown' so we must ensure that the fields are enabled (to disable the traps) if we are entering the kernel at EL1. The APK field disables PAuth instruction traps and the API field disables PAuth register traps Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer authentication is supported by the hardware. The runtime checks require a second temporary register, so add this to the EL1 transition macro signature and update 2 call sites. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
c48fec6e |
|
12-Jul-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Initialize CNTFRQ if at highest exception level CNTFRQ_EL0 is only writable from the highest supported exception level on the platform. For Armv8-A, this is typically EL3, but technically EL2 and EL3 are optional so it may need to be initialized at EL2 or EL1. For Armv8-R, the highest exception level is always EL2. This patch moves the initialization outside of the switch_el block and uses a new macro branch_if_not_highest_el which dynamically detects whether it is at the highest supported exception level. Linux's docs state that CNTFRQ_EL0 should be initialized by the bootloader. If not set, the the U-Boot prompt countdown hangs. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
2740edaf |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove set_dacr/get_dacr functions Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel <ardb@kernel.org> Serie-cc: R Sricharan <r.sricharan@ti.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
9b39d249 |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: cosmetic: align TTB_SECT define value Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
342e1abd |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
42d0d422 |
|
28-Nov-2020 |
Ovidiu Panait <ovidiu.panait@windriver.com> |
common: board_r: Drop initr_noncached wrapper Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6744ace5 |
|
06-Jul-2020 |
Ard Biesheuvel <ardb@kernel.org> |
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
c48fec6e |
|
12-Jul-2021 |
Peter Hoyes <Peter.Hoyes@arm.com> |
armv8: Initialize CNTFRQ if at highest exception level CNTFRQ_EL0 is only writable from the highest supported exception level on the platform. For Armv8-A, this is typically EL3, but technically EL2 and EL3 are optional so it may need to be initialized at EL2 or EL1. For Armv8-R, the highest exception level is always EL2. This patch moves the initialization outside of the switch_el block and uses a new macro branch_if_not_highest_el which dynamically detects whether it is at the highest supported exception level. Linux's docs state that CNTFRQ_EL0 should be initialized by the bootloader. If not set, the the U-Boot prompt countdown hangs. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> |
#
2740edaf |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove set_dacr/get_dacr functions Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel <ardb@kernel.org> Serie-cc: R Sricharan <r.sricharan@ti.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
9b39d249 |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: cosmetic: align TTB_SECT define value Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
342e1abd |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
42d0d422 |
|
28-Nov-2020 |
Ovidiu Panait <ovidiu.panait@windriver.com> |
common: board_r: Drop initr_noncached wrapper Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6744ace5 |
|
06-Jul-2020 |
Ard Biesheuvel <ardb@kernel.org> |
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
2740edaf |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove set_dacr/get_dacr functions Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel <ardb@kernel.org> Serie-cc: R Sricharan <r.sricharan@ti.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
9b39d249 |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: cosmetic: align TTB_SECT define value Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
342e1abd |
|
05-Feb-2021 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGH The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> |
#
42d0d422 |
|
28-Nov-2020 |
Ovidiu Panait <ovidiu.panait@windriver.com> |
common: board_r: Drop initr_noncached wrapper Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6744ace5 |
|
06-Jul-2020 |
Ard Biesheuvel <ardb@kernel.org> |
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
42d0d422 |
|
28-Nov-2020 |
Ovidiu Panait <ovidiu.panait@windriver.com> |
common: board_r: Drop initr_noncached wrapper Add a return value to noncached_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6744ace5 |
|
06-Jul-2020 |
Ard Biesheuvel <ardb@kernel.org> |
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
6744ace5 |
|
06-Jul-2020 |
Ard Biesheuvel <ardb@kernel.org> |
arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently defined as no-allocate for both reads and writes, which deviates from the non-LPAE definition, and mostly defeats the purpose of enabling the caches in the first place. So align LPAE with !LPAE, and enable allocate-on-read for both. And while at it, add some clarification about the meaning of the chosen values. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
d877f8fd |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: provide a function for boards init code to modify MMU virtual-physical map Provide function for setting arbitrary virtual-physical MMU mapping and cache settings for the given region. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
f5a9fcc6 |
|
03-Jun-2020 |
Marek Szyprowski <m.szyprowski@samsung.com> |
arm: update comments to the common style Update the comments in include/asm/system.h to the common style. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
22a4e006 |
|
27-May-2020 |
Heinrich Schuchardt <xypron.glpk@gmx.de> |
arm: use correct argument size of special registers Compiling with clang on ARMv8 shows errors like: ./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w" asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); ^~ %w0 These errors are due to using an incorrect size for the variables used for writing to and reading from special registers which have 64 bits on ARMv8. Mask off reserved bits when reading the exception level. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
9f8aa0fb |
|
19-May-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI arch/arm/include/asm/system.h declares psci_arch_init(), but it is surrounded by #ifdef CONFIG_ARMV8_PSCI. psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing function declaration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
c3dc39a2 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
arm: Don't include common.h in header files It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
2e8d68e2 |
|
24-Apr-2020 |
Patrick Delaunay <patrick.delaunay@st.com> |
arm: caches: add DCACHE_DEFAULT_OPTION Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
41acbc53 |
|
22-Nov-2019 |
Rajesh Ravi <rajesh.ravi@broadcom.com> |
arm: cpu: armv8: add support for arm psci reset2. Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@csgraf.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
e21e3ffd |
|
22-Jul-2019 |
Patrick Delaunay <patrick.delaunay@st.com> |
psci: Fix warnings when compiling with W=1 This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> |
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> |
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de> |
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@suse.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@suse.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de> |
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> |
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> |
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com> |
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com> |
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> |
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> |
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com> |
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com> |
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> |
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> |
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn> |
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn> |
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> |
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com> |
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> |
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |
#
a7aab5bc |
|
20-Aug-2018 |
Chee Hong Ang <chee.hong.ang@intel.com> |
ARMv8: Enable all asynchronous abort exceptions taken to EL3 Allow EL3 to handle all the External Abort and SError interrupt exception occur in all exception levels. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
|
#
acf15001 |
|
26-Apr-2018 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under armv7 folder. This led to a misconception of creating separate folders for armv7m and armv7r. There is no reason to create separate folder for other armv7 based architectures when it can co-exist with few Kconfig symbols. As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and can co exist in the same folder. Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Suggested-by: Alexander Graf <agraf@suse.de> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
#
7776cc01 |
|
10-Oct-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
arm: make save_boot_params_ret prototype visible for AArch64 The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
|
#
fb97b862 |
|
28-Sep-2017 |
York Sun <york.sun@nxp.com> |
armv8: layerscape: Enable falcon boot Add jump_to_image_linux() for arm64. Add "noreturn" flag to armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon boot. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Łukasz Majewski <lukma@denx.de> Tested-by: Łukasz Majewski <lukma@denx.de>
|
#
6775a820 |
|
05-Apr-2017 |
Simon Glass <sjg@chromium.org> |
arm: Support cache invalidate At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
7f9b9f31 |
|
06-Mar-2017 |
York Sun <york.sun@nxp.com> |
armv8: mmu: Add a function to change mapping attributes Function mmu_change_region_attr() is added to change existing mapping with updated PXN, UXN and memory type. This is a break-before-make process during which the mapping becomes fault (invalid) before final attributres are set. Signed-off-by: York Sun <york.sun@nxp.com>
|
#
7c5e1feb |
|
16-Jan-2017 |
Alison Wang <b18965@freescale.com> |
armv8: aarch64: Fix the warning about x1-x3 nonzero issue For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
9a561753 |
|
07-Dec-2016 |
macro.wave.z@gmail.com <macro.wave.z@gmail.com> |
ARMv8: Setup PSCI memory and device tree Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
3db86f4b |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
ec6617c3 |
|
09-Nov-2016 |
Alison Wang <b18965@freescale.com> |
armv8: Support loading 32-bit OS in AArch32 execution state To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
|
#
06d43c80 |
|
29-Oct-2016 |
Keerthy <j-keerthy@ti.com> |
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
1ab557a0 |
|
19-Oct-2016 |
Stephen Warren <swarren@nvidia.com> |
armv8: add hooks for all cache-wide operations SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
|
#
3ee655ed |
|
16-Aug-2016 |
Alexander Graf <agraf@suse.de> |
arm: Add PSCI shutdown function Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
51bfb5b6 |
|
16-Aug-2016 |
Alexander Graf <agraf@suse.de> |
arm: Disable HVC PSCI calls by default All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d31d4a2d |
|
13-Sep-2016 |
Keerthy <j-keerthy@ti.com> |
ARM: Introduce function to switch to hypervisor mode On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way. Cc: beagleboard-x15@googlegroups.com Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
|
#
a78cd861 |
|
01-Aug-2016 |
Tom Rini <trini@konsulko.com> |
ARM: Rework and correct barrier definitions As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5a07abb3 |
|
08-May-2016 |
Beniamino Galvani <b.galvani@gmail.com> |
arm: implement generic PSCI reset call for armv8 Add a psci_system_reset() which calls the SYSTEM_RESET function of PSCI 0.2 and can be used by boards that support it to implement reset_cpu(). Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
d990f5c8 |
|
16-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm: Add support for HYP mode and LPAE page tables We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de>
|
#
53eb45ef |
|
16-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Add 32bit arm compatible dcache definitions We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de>
|
#
7985cdf7 |
|
03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Remove non-full-va map code By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
|
#
5e2ec773 |
|
03-Mar-2016 |
Alexander Graf <agraf@suse.de> |
arm64: Make full va map code more dynamic The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de>
|
#
8890c2fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Remove S bit from MMU section entry Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org>
|
#
a592e6fb |
|
29-Dec-2015 |
Marek Vasut <marex@denx.de> |
arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7 The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org>
|
#
a5b9fa30 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
|
#
94f7ff36 |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: New MMU setup code allowing to use 48+ bits PA/VA This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
|
#
ba5648cd |
|
14-Oct-2015 |
Sergey Temerkhanov <s.temerkhanov@gmail.com> |
armv8: Add read_mpidr() function This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
88f965d7 |
|
05-Oct-2015 |
Stephen Warren <swarren@nvidia.com> |
armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com>
|
#
53fd4b8c |
|
08-Sep-2015 |
Alison Wang <b18965@freescale.com> |
arm: mmu: Add missing volatile for reading SCTLR register Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. (http://comments.gmane.org/gmane.linux.linaro.toolchain/5163) Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. Signed-off-by: Alison Wang <alison.wang@freescale.com>
|
#
dad17fd5 |
|
26-Jun-2015 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
armv8: caches: Added routine to set non cacheable region Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
|
#
55199121 |
|
04-May-2015 |
Simon Glass <sjg@chromium.org> |
arm: Add a prototype for save_boot_params_ret() It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
|
#
73169874 |
|
20-Apr-2015 |
Ian Campbell <ijc@hellion.org.uk> |
tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
|
#
97840b5d |
|
24-Mar-2015 |
Bryan Brinsko <bryan.brinsko@rockwellcollins.com> |
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
|
#
dcd468b8 |
|
06-Jan-2015 |
York Sun <yorksun@freescale.com> |
armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
|
#
e11c6c27 |
|
07-Feb-2015 |
Simon Glass <sjg@chromium.org> |
arm: Allow lr to be saved by board code The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
#
1dfdd9ba |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
|
#
ed710457 |
|
09-Dec-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: Implement non-cached memory support Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org>
|
#
25026fa9 |
|
26-Aug-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: cache-cp15: Use more accurate types size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com>
|
#
ff7e9700 |
|
14-Sep-2014 |
Marek Vasut <marex@denx.de> |
arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
|
#
2f78eae5 |
|
23-Jun-2014 |
York Sun <yorksun@freescale.com> |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
|
#
1e6ad55c |
|
26-Feb-2014 |
York Sun <yorksun@freescale.com> |
armv8/cache: Change cache invalidate and flush function When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
|
#
0ae76531 |
|
13-Dec-2013 |
David Feng <fenghua@phytium.com.cn> |
arm64: core support Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn>
|
#
de63ac27 |
|
04-Mar-2013 |
R Sricharan <r.sricharan@ti.com> |
ARM: mmu: Set domain permissions to client access The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
|
#
2ff467c0 |
|
02-Dec-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: add wfi assembly macro Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
|
#
0dde7f53 |
|
17-Oct-2012 |
Simon Glass <sjg@chromium.org> |
arm: Add control over cachability of memory regions Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
|
#
819833af |
|
12-Apr-2010 |
Peter Tyser <ptyser@xes-inc.com> |
Move architecture-specific includes to arch/$ARCH/include/asm This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
|