History log of /seL4-camkes-master/projects/musllibc/arch/riscv_sel4/bits/alltypes.h.in
Revision Date Author Comments
# 48c4d118 04-Apr-2018 Anna Lyons <Anna.Lyons@data61.csiro.au>

riscv: define _Addr and __sysinfo as int for 32bit


# f02a8407 04-Apr-2018 Anna Lyons <Anna.Lyons@data61.csiro.au>

riscv: build on 32-bit


# ad0e98ed 03-Apr-2018 Kent McLeod <Kent.Mcleod@data61.csiro.au>

RISC-V: Use pthread typedefs from x86_64 for now

They at least have the union definitions with correct sizes. Given that
we don't support TLS for RISC-V the sizes of these don't really matter
for now.


# f548fc36 02-Apr-2018 Kent McLeod <Kent.Mcleod@data61.csiro.au>

RISC-V: Revert pthread_impl definitions


# 23252db4 02-Apr-2018 Kent McLeod <Kent.Mcleod@data61.csiro.au>

RISC-V: Fix core type definitions and sizes


# 2435f79d 30-Jul-2016 Hesham Almatary <hesham.almatary@data61.csiro.au>

RISC-V port