Drop the first argument of intr_establish().

Instead, require all callers to put the right value in the ih_pil field, and
have intr_establish() trust them rather than assigning this field again from
its first argument.

ok claudio@ kettenis@

add support for bypassing iommu translation

managing the translation table entries (TTEs) on an iommu is not
free, and is in fact extremely expensive on some platforms. the
flip side of this is that forcing dma through TTEs does provide
some safety and can help during the development of drivers. however,
this has been less true in recent years than it used to be and is
less of a concern now, especially considering the performance
differences on some platforms.

devices have to create dmamaps with BUS_DMA_64BIT to bypass the
iommu because the memory window presented to hardware with direct
access to memory is at an extremely high address. there's no 32bit
bypass access to memory, it has to go through TTEs otherwise.

on an m4000 there are several orders of magnitude performance
difference between a driver with BUS_DMA_64BIT set and one without
it.

hilariously, sun used a pci bridge on a whole generation of machines
that had broken support for dma addresses over 40 bits (or around
there), so devices behind those pci bridges need to have their
dmamap_creates intercepted and any potential BUS_DMA_64BIT flags
cleared on the way to the iommu drivers. this affects at least v215,
v245, and v445, and probably u25s and u45s. it probably explains
why all their onboard nics and disk controllers feel super slow,
and why there was a meme at sun that bcopy was cheaper than dma
when moving packets on and off a nic.

ok kettenis@ deraadt@

tweak sparc64 membars as a step toward making them usable in userland.

specifically, dont rely on magic in ctlreg to implement membars. moving
that to atomic.h would add a lot of pollution to the namespace, so
move to passing the membar options to a single __membar macro.

this tweaks everything that was using the ctlreg backend to either use
an appropriate membar_foo(), or to use __membar() in the MD code.

ok kettenis@

Convert %q to %ll in format strings

ok natano@ krw@

add a size argument to free. will be used soon, but for now default to 0.
after discussions with beck deraadt kettenis.

Schizo registers are all 64-bit, so use u_int64_t to store them and print them
using %llx/%llb.

Implement support for running interrupt handlers without taking the kernel
lock, by adding a new BUS_INTR_ESTABLISH_MPSAFE flag for use with the
(sparc64-specific) bus_intr_establish(9) interface. Add support for this
flag to schizo(4); other bus drivers will ignore it for now. While there,
remove the BUS_INTR_ESTABLISH_FASTTRAP flag which serves no purpose.

Handle pci_conf_read() faults on reading non-existent registers that result
in master aborts. Return 0xffffffff to emulate what happens on non-perfect
architectures in that case.

ok deraadt@

Fix some inconsistencies in how we build 64-bit addresses from OF properties.

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

bzero pci attach args

ok deraadt@, miod@

make various strings ("can't map mem space" and similar) more consistent
between instances, saving space in the kernel. feedback from many (some
incorporated, some left for future work).

ok deraadt, kettenis, "why not" miod.

Make IOMMU code use the generic _bus_dmamem_map() and _bus_dmamem_unmap().

Add missing #ifdef DDB around prototyupe.

Make the "machine xir" ddb command work on machines with Tomatillo
schizo(4) variants.

Add sparc_bus_addr function for schizo to allow CardBus to work.

ok kettenis@

Match on XMITS (which is a PCI-X Schizo variant found on Sun Fire
E2900/E4900/E6900/E20K/E25K systems). There's a fairly good chance it'll
just work.

Make host bridges provide their own implementation of pci_conf_read() and
pci_conf_write() and give pyro(4) an implementation suitable for PCIe. For
psycho(4) and schizo(4), go back to the origional implementation. This gets
rid of the 'tagshift' member of pci_chipset_tag_t, and clears the way for
sun4v.

Fix printf format string.

malloc+bzero -> malloc+M_ZERO. Use 'malloc(sizeof(*p) ...' idiom.

This completes my bzero/memset(,0,) -> M_ZERO sweep of the tree.

ok kettenis@

A few trailing bzero/memset -> M_ZERO occurrences, cast removal and
size(*p) usage. This should be the last of the simple malloc()
changes.

Only the most obvious bzero() -> M_ZERO changes. No cast changes, no
MALLOC/FREE, etc. Just adding M_ZERO to malloc() and deleting an
immediately adjacent bzero().

Print a bit more information in the safari interrupt handler. Get rid of
function names starting with an underscore while I'm there.

Print safari error log register if we get a safari interrupt.

Establish pci error interrupt after we're done fiddling with schizo's registers
instead of when we're halfway through.

Deal with zero wraparound in DVMA range checks;
Fix default DVMA range for Schizo's with no "virtual-dma" property;
Add TSB size indicator to Schizo & Psycho debugging messages.

ok jason@

Do not panic on non-fatal iommu errors.

Really print iommu TFAR (instead of CTRL again).

Clear error bits in PCI command/status register before establishing PCI error
handler.

Provide a bit more diagnostic information in the PCI error handler.

Print Schizo/Tomatillo version number.

According to the OpenSolaris sources, the DTO bits are really MMU bit.
Add the real DTO bits for Tomatillo.

change schizo/psycho interrupts to be xname:what instead of ugly names
seen previously; discussed with kettenis

Make pci subsystem aware of domains. Each host bridge gets assigned a unique
domain number such that we can distinguish between busses with the same bus
number that are behind different host bridges. Domains can be accessed by
using different device nodes.

ok deraadt@

Use appropriate macros to decode IGN.

Use the correct IGN for the B side of schizo. Makes interrupts actually work
in the PCI slot of the v210.

ok jason@

one more dmesg tweak

clean dmesg output for iommu more; tested miod dlg

Some machines lack the virtual-dma property. In that case, go back
to the 128KB assumption, until we find out another way to determine
the space. Damn.

cleanup dmesg logging for iommu goo, make it follow the standard form

look at "virtual-dma" property to decide where the iommu address space
is, instead of having iommu_init() decide

keep track of what is a schizo and what is tomatillo

Fix interrupt mapping. This now seems to work on all machines, even with
pci cards that have a pci-pci bridge and lack fcode.

tested by many, ok jason@, dlg@

match tomatillo varient (not yet fully working)

- clear the PCI_AFSR during init
- set up the interrupts more correctly
- print errors nicer

latch the AFSR/AFAR -before- reading the PCI control/status register

do a better job of setting up the PBM. Doesn't fix the PIO faults we're
seeing, I"m not convinced they're fixable any more.

- stop using magic constants for the onboard error INOs (one was wrong anyway)
- setup pci error interrupts and do an interpretive dance with the registers

enable error interrupts and install handlers for same (the handlers don't do much yet)

oops, nuke debugging stuff

- Implement schizo_intr_map (mainly to | in the agentid).
- get correct IGN for intr_establish
all of this is from kettenis and henric, I'm just cleaning it up and committing
the easy bits

don't hardcode the iova... it uses the same scheme as the sbus machines
(cd0 at scsibus0 at siop0 now attaches on the blade2k)

rev 1.86

make the "generic" PCI bus enumeration code the standard case which
gets used if nothing else is defined in MD headers,
introduce a "PCI_MACHDEP_ENUMERATE_BUS" CPP definition which can
be used by MD headers (just 1 port atm) to plug in special code

rev 1.62

* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).

rev 1.59

Split the code that enumerates the PCI bus and that actually probes
for a device into two functions:

* pci_probe_device() actually probes/attaches the device specified
by the provide pcitag_t.

* pci_enumerate_bus() enumerates the bus, and calls pci_probe_device()
for each device on the bus. A pci_enumerate_bus_generic() is provided
which implements the old method of doing this: If something found at
dev0/func0, determine number of functions and probe each one.

From NetBSD

ok kettenis@

Tested on a good number of amd64/i386/macppc/sparc64 systems

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.

From NetBSD

ok grange@ kettenis@

Add a "where" argument to the sparc64 interrupt code. This lets us
associate a name with each interrupt handler. This is not visible
outside the kernel (yet).

ok jason@

Much of the sbus, psycho, and schizo bus_dma code is the same, so let's
call the real implementation functions directly instead of duplicating
lots of code that only calls the real stuff anyway.

tested by miod@ henning@
ok jason@

nuke clause 3 & 4 (with henric's permission)

nuke debugging stuff

get the offset of the config space correct, now to figure out why the rtc is unhappy.

branches: 1.11.4;
The existing IOMMU code had a rounding problem that was most noticeable
on faster systems under heavy network load. This replaces some of the
unreadable iommu functions with something a little less dense and a lot
less crash prone.

The bus_dma function pointer/cookie handling was broken. Change them
to work like the stacked bus_space drivers (where "work" is the key
word).

Tested my many (thanks).

ok jason@ deraadt@

rearrange allocations and such so that this actually attaches (still panics
when attaching the pcibus... Still working on it =)

Add support for the Sun Enterprise 450
Reduce the size of a GENERIC kernel by ~190k
Remove the nasty pointer/bus_space_handle_t casts
Adds debug bus_space code including the ability to trace
bus operations (it actually works now).

The following rules are now followed (and verfified by the debug
code):

1. A "bus_space_handle_t" may only be used with the
"bus_space_tag_t" that created it.
2. Only "bus_space_map()" may create "bus_space_handle_t"s.
3. A "bus_space_handle_t" may not be modified after it has
been created (other than being destroyed by "bus_space_unmap()").


Thanks to help from mcbride, marc, jason, drahn, to anyone that might
have slipped my mind at the moment.

ok jason@, deraadt@

Don't use a global variable to determine which pci_conf* function to call,
store function pointers in the pci_chipset_tag_t (ie. fix an ugly hack
I did during the hackathon last year).

add support for mapping interrupts.

nuke debugging cruft

add support for schizo streaming buffers (per PBM), but leave the buffers disabled for now

- Add support for both of the schizo iommu's(There is an iommu per pbm)
- const the cfattach
- clean
- deal with the fact that the register property doesn't reflect the true
length of the register set (grr!)
- move away from home grown read/write_8 and use bus_space where possible

add mmap implementation and skeleton interrupt mapping

branches: 1.2.2;
Move stuff around like a crazy man... (split into var/reg)

Initial (not quite fully working) driver for the schizo on the blade1000

add support for bypassing iommu translation

managing the translation table entries (TTEs) on an iommu is not
free, and is in fact extremely expensive on some platforms. the
flip side of this is that forcing dma through TTEs does provide
some safety and can help during the development of drivers. however,
this has been less true in recent years than it used to be and is
less of a concern now, especially considering the performance
differences on some platforms.

devices have to create dmamaps with BUS_DMA_64BIT to bypass the
iommu because the memory window presented to hardware with direct
access to memory is at an extremely high address. there's no 32bit
bypass access to memory, it has to go through TTEs otherwise.

on an m4000 there are several orders of magnitude performance
difference between a driver with BUS_DMA_64BIT set and one without
it.

hilariously, sun used a pci bridge on a whole generation of machines
that had broken support for dma addresses over 40 bits (or around
there), so devices behind those pci bridges need to have their
dmamap_creates intercepted and any potential BUS_DMA_64BIT flags
cleared on the way to the iommu drivers. this affects at least v215,
v245, and v445, and probably u25s and u45s. it probably explains
why all their onboard nics and disk controllers feel super slow,
and why there was a meme at sun that bcopy was cheaper than dma
when moving packets on and off a nic.

ok kettenis@ deraadt@

tweak sparc64 membars as a step toward making them usable in userland.

specifically, dont rely on magic in ctlreg to implement membars. moving
that to atomic.h would add a lot of pollution to the namespace, so
move to passing the membar options to a single __membar macro.

this tweaks everything that was using the ctlreg backend to either use
an appropriate membar_foo(), or to use __membar() in the MD code.

ok kettenis@

Convert %q to %ll in format strings

ok natano@ krw@

add a size argument to free. will be used soon, but for now default to 0.
after discussions with beck deraadt kettenis.

Schizo registers are all 64-bit, so use u_int64_t to store them and print them
using %llx/%llb.

Implement support for running interrupt handlers without taking the kernel
lock, by adding a new BUS_INTR_ESTABLISH_MPSAFE flag for use with the
(sparc64-specific) bus_intr_establish(9) interface. Add support for this
flag to schizo(4); other bus drivers will ignore it for now. While there,
remove the BUS_INTR_ESTABLISH_FASTTRAP flag which serves no purpose.

Handle pci_conf_read() faults on reading non-existent registers that result
in master aborts. Return 0xffffffff to emulate what happens on non-perfect
architectures in that case.

ok deraadt@

Fix some inconsistencies in how we build 64-bit addresses from OF properties.

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

bzero pci attach args

ok deraadt@, miod@

make various strings ("can't map mem space" and similar) more consistent
between instances, saving space in the kernel. feedback from many (some
incorporated, some left for future work).

ok deraadt, kettenis, "why not" miod.

Make IOMMU code use the generic _bus_dmamem_map() and _bus_dmamem_unmap().

Add missing #ifdef DDB around prototyupe.

Make the "machine xir" ddb command work on machines with Tomatillo
schizo(4) variants.

Add sparc_bus_addr function for schizo to allow CardBus to work.

ok kettenis@

Match on XMITS (which is a PCI-X Schizo variant found on Sun Fire
E2900/E4900/E6900/E20K/E25K systems). There's a fairly good chance it'll
just work.

Make host bridges provide their own implementation of pci_conf_read() and
pci_conf_write() and give pyro(4) an implementation suitable for PCIe. For
psycho(4) and schizo(4), go back to the origional implementation. This gets
rid of the 'tagshift' member of pci_chipset_tag_t, and clears the way for
sun4v.

Fix printf format string.

malloc+bzero -> malloc+M_ZERO. Use 'malloc(sizeof(*p) ...' idiom.

This completes my bzero/memset(,0,) -> M_ZERO sweep of the tree.

ok kettenis@

A few trailing bzero/memset -> M_ZERO occurrences, cast removal and
size(*p) usage. This should be the last of the simple malloc()
changes.

Only the most obvious bzero() -> M_ZERO changes. No cast changes, no
MALLOC/FREE, etc. Just adding M_ZERO to malloc() and deleting an
immediately adjacent bzero().

Print a bit more information in the safari interrupt handler. Get rid of
function names starting with an underscore while I'm there.

Print safari error log register if we get a safari interrupt.

Establish pci error interrupt after we're done fiddling with schizo's registers
instead of when we're halfway through.

Deal with zero wraparound in DVMA range checks;
Fix default DVMA range for Schizo's with no "virtual-dma" property;
Add TSB size indicator to Schizo & Psycho debugging messages.

ok jason@

Do not panic on non-fatal iommu errors.

Really print iommu TFAR (instead of CTRL again).

Clear error bits in PCI command/status register before establishing PCI error
handler.

Provide a bit more diagnostic information in the PCI error handler.

Print Schizo/Tomatillo version number.

According to the OpenSolaris sources, the DTO bits are really MMU bit.
Add the real DTO bits for Tomatillo.

change schizo/psycho interrupts to be xname:what instead of ugly names
seen previously; discussed with kettenis

Make pci subsystem aware of domains. Each host bridge gets assigned a unique
domain number such that we can distinguish between busses with the same bus
number that are behind different host bridges. Domains can be accessed by
using different device nodes.

ok deraadt@

Use appropriate macros to decode IGN.

Use the correct IGN for the B side of schizo. Makes interrupts actually work
in the PCI slot of the v210.

ok jason@

one more dmesg tweak

clean dmesg output for iommu more; tested miod dlg

Some machines lack the virtual-dma property. In that case, go back
to the 128KB assumption, until we find out another way to determine
the space. Damn.

cleanup dmesg logging for iommu goo, make it follow the standard form

look at "virtual-dma" property to decide where the iommu address space
is, instead of having iommu_init() decide

keep track of what is a schizo and what is tomatillo

Fix interrupt mapping. This now seems to work on all machines, even with
pci cards that have a pci-pci bridge and lack fcode.

tested by many, ok jason@, dlg@

match tomatillo varient (not yet fully working)

- clear the PCI_AFSR during init
- set up the interrupts more correctly
- print errors nicer

latch the AFSR/AFAR -before- reading the PCI control/status register

do a better job of setting up the PBM. Doesn't fix the PIO faults we're
seeing, I"m not convinced they're fixable any more.

- stop using magic constants for the onboard error INOs (one was wrong anyway)
- setup pci error interrupts and do an interpretive dance with the registers

enable error interrupts and install handlers for same (the handlers don't do much yet)

oops, nuke debugging stuff

- Implement schizo_intr_map (mainly to | in the agentid).
- get correct IGN for intr_establish
all of this is from kettenis and henric, I'm just cleaning it up and committing
the easy bits

don't hardcode the iova... it uses the same scheme as the sbus machines
(cd0 at scsibus0 at siop0 now attaches on the blade2k)

rev 1.86

make the "generic" PCI bus enumeration code the standard case which
gets used if nothing else is defined in MD headers,
introduce a "PCI_MACHDEP_ENUMERATE_BUS" CPP definition which can
be used by MD headers (just 1 port atm) to plug in special code

rev 1.62

* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).

rev 1.59

Split the code that enumerates the PCI bus and that actually probes
for a device into two functions:

* pci_probe_device() actually probes/attaches the device specified
by the provide pcitag_t.

* pci_enumerate_bus() enumerates the bus, and calls pci_probe_device()
for each device on the bus. A pci_enumerate_bus_generic() is provided
which implements the old method of doing this: If something found at
dev0/func0, determine number of functions and probe each one.

From NetBSD

ok kettenis@

Tested on a good number of amd64/i386/macppc/sparc64 systems

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.

From NetBSD

ok grange@ kettenis@

Add a "where" argument to the sparc64 interrupt code. This lets us
associate a name with each interrupt handler. This is not visible
outside the kernel (yet).

ok jason@

Much of the sbus, psycho, and schizo bus_dma code is the same, so let's
call the real implementation functions directly instead of duplicating
lots of code that only calls the real stuff anyway.

tested by miod@ henning@
ok jason@

nuke clause 3 & 4 (with henric's permission)

nuke debugging stuff

get the offset of the config space correct, now to figure out why the rtc is unhappy.

branches: 1.11.4;
The existing IOMMU code had a rounding problem that was most noticeable
on faster systems under heavy network load. This replaces some of the
unreadable iommu functions with something a little less dense and a lot
less crash prone.

The bus_dma function pointer/cookie handling was broken. Change them
to work like the stacked bus_space drivers (where "work" is the key
word).

Tested my many (thanks).

ok jason@ deraadt@

rearrange allocations and such so that this actually attaches (still panics
when attaching the pcibus... Still working on it =)

Add support for the Sun Enterprise 450
Reduce the size of a GENERIC kernel by ~190k
Remove the nasty pointer/bus_space_handle_t casts
Adds debug bus_space code including the ability to trace
bus operations (it actually works now).

The following rules are now followed (and verfified by the debug
code):

1. A "bus_space_handle_t" may only be used with the
"bus_space_tag_t" that created it.
2. Only "bus_space_map()" may create "bus_space_handle_t"s.
3. A "bus_space_handle_t" may not be modified after it has
been created (other than being destroyed by "bus_space_unmap()").


Thanks to help from mcbride, marc, jason, drahn, to anyone that might
have slipped my mind at the moment.

ok jason@, deraadt@

Don't use a global variable to determine which pci_conf* function to call,
store function pointers in the pci_chipset_tag_t (ie. fix an ugly hack
I did during the hackathon last year).

add support for mapping interrupts.

nuke debugging cruft

add support for schizo streaming buffers (per PBM), but leave the buffers disabled for now

- Add support for both of the schizo iommu's(There is an iommu per pbm)
- const the cfattach
- clean
- deal with the fact that the register property doesn't reflect the true
length of the register set (grr!)
- move away from home grown read/write_8 and use bus_space where possible

add mmap implementation and skeleton interrupt mapping

branches: 1.2.2;
Move stuff around like a crazy man... (split into var/reg)

Initial (not quite fully working) driver for the schizo on the blade1000

tweak sparc64 membars as a step toward making them usable in userland.

specifically, dont rely on magic in ctlreg to implement membars. moving
that to atomic.h would add a lot of pollution to the namespace, so
move to passing the membar options to a single __membar macro.

this tweaks everything that was using the ctlreg backend to either use
an appropriate membar_foo(), or to use __membar() in the MD code.

ok kettenis@

Convert %q to %ll in format strings

ok natano@ krw@

add a size argument to free. will be used soon, but for now default to 0.
after discussions with beck deraadt kettenis.

Schizo registers are all 64-bit, so use u_int64_t to store them and print them
using %llx/%llb.

Implement support for running interrupt handlers without taking the kernel
lock, by adding a new BUS_INTR_ESTABLISH_MPSAFE flag for use with the
(sparc64-specific) bus_intr_establish(9) interface. Add support for this
flag to schizo(4); other bus drivers will ignore it for now. While there,
remove the BUS_INTR_ESTABLISH_FASTTRAP flag which serves no purpose.

Handle pci_conf_read() faults on reading non-existent registers that result
in master aborts. Return 0xffffffff to emulate what happens on non-perfect
architectures in that case.

ok deraadt@

Fix some inconsistencies in how we build 64-bit addresses from OF properties.

Introduce a new pci routine, pci_conf_size(), which returns the size of a
given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

bzero pci attach args

ok deraadt@, miod@

make various strings ("can't map mem space" and similar) more consistent
between instances, saving space in the kernel. feedback from many (some
incorporated, some left for future work).

ok deraadt, kettenis, "why not" miod.

Make IOMMU code use the generic _bus_dmamem_map() and _bus_dmamem_unmap().

Add missing #ifdef DDB around prototyupe.

Make the "machine xir" ddb command work on machines with Tomatillo
schizo(4) variants.

Add sparc_bus_addr function for schizo to allow CardBus to work.

ok kettenis@

Match on XMITS (which is a PCI-X Schizo variant found on Sun Fire
E2900/E4900/E6900/E20K/E25K systems). There's a fairly good chance it'll
just work.

Make host bridges provide their own implementation of pci_conf_read() and
pci_conf_write() and give pyro(4) an implementation suitable for PCIe. For
psycho(4) and schizo(4), go back to the origional implementation. This gets
rid of the 'tagshift' member of pci_chipset_tag_t, and clears the way for
sun4v.

Fix printf format string.

malloc+bzero -> malloc+M_ZERO. Use 'malloc(sizeof(*p) ...' idiom.

This completes my bzero/memset(,0,) -> M_ZERO sweep of the tree.

ok kettenis@

A few trailing bzero/memset -> M_ZERO occurrences, cast removal and
size(*p) usage. This should be the last of the simple malloc()
changes.

Only the most obvious bzero() -> M_ZERO changes. No cast changes, no
MALLOC/FREE, etc. Just adding M_ZERO to malloc() and deleting an
immediately adjacent bzero().

Print a bit more information in the safari interrupt handler. Get rid of
function names starting with an underscore while I'm there.

Print safari error log register if we get a safari interrupt.

Establish pci error interrupt after we're done fiddling with schizo's registers
instead of when we're halfway through.

Deal with zero wraparound in DVMA range checks;
Fix default DVMA range for Schizo's with no "virtual-dma" property;
Add TSB size indicator to Schizo & Psycho debugging messages.

ok jason@

Do not panic on non-fatal iommu errors.

Really print iommu TFAR (instead of CTRL again).

Clear error bits in PCI command/status register before establishing PCI error
handler.

Provide a bit more diagnostic information in the PCI error handler.

Print Schizo/Tomatillo version number.

According to the OpenSolaris sources, the DTO bits are really MMU bit.
Add the real DTO bits for Tomatillo.

change schizo/psycho interrupts to be xname:what instead of ugly names
seen previously; discussed with kettenis

Make pci subsystem aware of domains. Each host bridge gets assigned a unique
domain number such that we can distinguish between busses with the same bus
number that are behind different host bridges. Domains can be accessed by
using different device nodes.

ok deraadt@

Use appropriate macros to decode IGN.

Use the correct IGN for the B side of schizo. Makes interrupts actually work
in the PCI slot of the v210.

ok jason@

one more dmesg tweak

clean dmesg output for iommu more; tested miod dlg

Some machines lack the virtual-dma property. In that case, go back
to the 128KB assumption, until we find out another way to determine
the space. Damn.

cleanup dmesg logging for iommu goo, make it follow the standard form

look at "virtual-dma" property to decide where the iommu address space
is, instead of having iommu_init() decide

keep track of what is a schizo and what is tomatillo

Fix interrupt mapping. This now seems to work on all machines, even with
pci cards that have a pci-pci bridge and lack fcode.

tested by many, ok jason@, dlg@

match tomatillo varient (not yet fully working)

- clear the PCI_AFSR during init
- set up the interrupts more correctly
- print errors nicer

latch the AFSR/AFAR -before- reading the PCI control/status register

do a better job of setting up the PBM. Doesn't fix the PIO faults we're
seeing, I"m not convinced they're fixable any more.

- stop using magic constants for the onboard error INOs (one was wrong anyway)
- setup pci error interrupts and do an interpretive dance with the registers

enable error interrupts and install handlers for same (the handlers don't do much yet)

oops, nuke debugging stuff

- Implement schizo_intr_map (mainly to | in the agentid).
- get correct IGN for intr_establish
all of this is from kettenis and henric, I'm just cleaning it up and committing
the easy bits

don't hardcode the iova... it uses the same scheme as the sbus machines
(cd0 at scsibus0 at siop0 now attaches on the blade2k)

rev 1.86

make the "generic" PCI bus enumeration code the standard case which
gets used if nothing else is defined in MD headers,
introduce a "PCI_MACHDEP_ENUMERATE_BUS" CPP definition which can
be used by MD headers (just 1 port atm) to plug in special code

rev 1.62

* Implement a machine-dependent pci_enumerate_bus() for sparc64 which
uses OFW device nodes to enumerate the bus. When a PCI bus that is
behind a bridge is attached, pci_attach_hook() allocates a new PCI
chipset tag for the new bus and sets it's "curnode" to the OFW node
of the bridge. This is used as a starting point when enumerating
that bus. Root busses get the OFW node of the host bridge (psycho).

rev 1.59

Split the code that enumerates the PCI bus and that actually probes
for a device into two functions:

* pci_probe_device() actually probes/attaches the device specified
by the provide pcitag_t.

* pci_enumerate_bus() enumerates the bus, and calls pci_probe_device()
for each device on the bus. A pci_enumerate_bus_generic() is provided
which implements the old method of doing this: If something found at
dev0/func0, determine number of functions and probe each one.

From NetBSD

ok kettenis@

Tested on a good number of amd64/i386/macppc/sparc64 systems

* Add "pcitag_t *pba_bridgetag" to pci_attach_args. This is set to
NULL for root PCI busses. For busses behind a bridge, it points to
a persistent copy of the bridge's pcitag_t. This can be very useful
for machine-dependent PCI bus enumeration code.

From NetBSD

ok grange@ kettenis@

Add a "where" argument to the sparc64 interrupt code. This lets us
associate a name with each interrupt handler. This is not visible
outside the kernel (yet).

ok jason@

Much of the sbus, psycho, and schizo bus_dma code is the same, so let's
call the real implementation functions directly instead of duplicating
lots of code that only calls the real stuff anyway.

tested by miod@ henning@
ok jason@

nuke clause 3 & 4 (with henric's permission)

nuke debugging stuff

get the offset of the config space correct, now to figure out why the rtc is unhappy.

branches: 1.11.4;
The existing IOMMU code had a rounding problem that was most noticeable
on faster systems under heavy network load. This replaces some of the
unreadable iommu functions with something a little less dense and a lot
less crash prone.

The bus_dma function pointer/cookie handling was broken. Change them
to work like the stacked bus_space drivers (where "work" is the key
word).

Tested my many (thanks).

ok jason@ deraadt@

rearrange allocations and such so that this actually attaches (still panics
when attaching the pcibus... Still working on it =)

Add support for the Sun Enterprise 450
Reduce the size of a GENERIC kernel by ~190k
Remove the nasty pointer/bus_space_handle_t casts
Adds debug bus_space code including the ability to trace
bus operations (it actually works now).

The following rules are now followed (and verfified by the debug
code):

1. A "bus_space_handle_t" may only be used with the
"bus_space_tag_t" that created it.
2. Only "bus_space_map()" may create "bus_space_handle_t"s.
3. A "bus_space_handle_t" may not be modified after it has
been created (other than being destroyed by "bus_space_unmap()").


Thanks to help from mcbride, marc, jason, drahn, to anyone that might
have slipped my mind at the moment.

ok jason@, deraadt@

Don't use a global variable to determine which pci_conf* function to call,
store function pointers in the pci_chipset_tag_t (ie. fix an ugly hack
I did during the hackathon last year).

add support for mapping interrupts.

nuke debugging cruft

add support for schizo streaming buffers (per PBM), but leave the buffers disabled for now

- Add support for both of the schizo iommu's(There is an iommu per pbm)
- const the cfattach
- clean
- deal with the fact that the register property doesn't reflect the true
length of the register set (grr!)
- move away from home grown read/write_8 and use bus_space where possible

add mmap implementation and skeleton interrupt mapping

branches: 1.2.2;
Move stuff around like a crazy man... (split into var/reg)

Initial (not quite fully working) driver for the schizo on the blade1000