#
b1956e2d |
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02-May-2024 |
Dave Jiang <dave.jiang@intel.com> |
PCI/CXL: Fail bus reset if upstream CXL Port has SBR masked Per CXL spec r3.1, sec 8.1.5.2, the Secondary Bus Reset (SBR) bit in the Bridge Control register of a CXL port has no effect unless the "Unmask SBR" bit is set. Return -ENOTTY if we attempt a bus reset on a device below a CXL Port where "Unmask SBR" is 0. Otherwise, the bus reset would appear to have succeeded even though setting the bridge SBR bit had no effect. Link: https://lore.kernel.org/linux-cxl/20240220203956.GA1502351@bhelgaas/ Link: https://lore.kernel.org/r/20240502165851.1948523-4-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> [bhelgaas: simplify commit log and comments] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
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#
eebab7e3 |
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06-Mar-2024 |
Alexey Kardashevskiy <aik@amd.com> |
PCI/DOE: Support discovery version 2 PCIe r6.1, sec 6.30.1.1 defines a "DOE Discovery Version" field in the DOE Discovery Request Data Object Contents (3rd DW) as: 15:8 DOE Discovery Version – must be 02h if the Capability Version in the Data Object Exchange Extended Capability is 02h or greater. Add support for the version on devices with the DOE v2 capability. Link: https://lore.kernel.org/r/20240307022006.3657433-1-aik@amd.com Signed-off-by: Alexey Kardashevskiy <aik@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
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#
ec302b11 |
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10-Oct-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/PME: Use FIELD_GET() Use FIELD_GET() to remove dependences on the field position, i.e., the shift value. No functional change intended. Link: https://lore.kernel.org/r/20231010204436.1000644-8-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
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#
e0701bd0 |
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10-Oct-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/ATS: Use FIELD_GET() Use FIELD_GET() to remove dependences on the field position, i.e., the shift value. No functional change intended. Link: https://lore.kernel.org/r/20231010204436.1000644-6-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
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#
d30fea25 |
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10-Oct-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/ATS: Show PASID Capability register width in bitmasks The PASID Capability and Control registers are both 16 bits wide. Use 16-bit wide constants in field names to match the register width. No functional change intended. Link: https://lore.kernel.org/r/20231010204436.1000644-5-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
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#
74f0b5ff |
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18-Oct-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
PCI/DPC: Use defines with DPC reason fields Add new defines for DPC reason fields and use them instead of literals. Link: https://lore.kernel.org/r/20231018113254.17616-7-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> [bhelgaas: shorten comments] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
9a9eec47 |
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18-Oct-2023 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/DPC: Use FIELD_GET() Use FIELD_GET() to remove dependencies on the field position, i.e., the shift value. No functional change intended. Link: https://lore.kernel.org/r/20231018113254.17616-5-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
92af77ca |
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24-Oct-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
PCI: dwc: Use FIELD_GET/PREP() Convert open-coded variants of PCI field access into FIELD_GET/PREP() to make the code easier to understand. Add two missing defines into pci_regs.h. Logically, the Max No-Snoop Latency Register is a separate word sized register in the PCIe spec, but the pre-existing LTR defines in pci_regs.h with dword long values seem to consider the registers together (the same goes for the only user). Thus, follow the custom and make the new values also take both word long LTR registers as a joint dword register. Link: https://lore.kernel.org/r/20231024110336.26264-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
1a11074b |
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15-Sep-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
PCI: Add PCI_L1SS_CTL2 fields Add L1 PM Substates Control 2 Register fields (PCI_L1SS_CTL2_*). Link: https://lore.kernel.org/r/20230915155752.84640-2-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
bdca03a2 |
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03-Oct-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
PCI: Add PCI_HEADER_TYPE_MFD definition Add PCI_HEADER_TYPE_MFD so we can replace literals in the code. Link: https://lore.kernel.org/r/20231003125300.5541-3-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
0b3dee60 |
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31-May-2023 |
Ben Dooks <ben-linux@fluff.org> |
PCI: Add PCI_EXT_CAP_ID_PL_32GT define Add the define for PCI_EXT_CAP_ID_PL_32GT for drivers that will want this whilst doing Gen5/Gen6 accesses. Link: https://lore.kernel.org/r/20230531095713.293229-1-ben.dooks@codethink.co.uk Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
248529ed |
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14-Feb-2023 |
Dave Jiang <dave.jiang@intel.com> |
cxl: add RAS status unmasking for CXL By default the CXL RAS mask registers bits are defaulted to 1's and suppress all error reporting. If the kernel has negotiated ownership of error handling for CXL then unmask the mask registers by writing 0s. PCI_EXP_DEVCTL capability is checked to see uncorrectable or correctable errors bits are set before unmasking the respective errors. Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_regs.h Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/167639402301.778884.12556849214955646539.stgit@djiang5-mobl3.local Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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#
e32e1e26 |
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19-Sep-2022 |
Vidya Sagar <vidyas@nvidia.com> |
PCI: Add PCI_PTM_CAP_RES macro Add macro defining Responder capable bit in Precision Time Measurement capability register. Link: https://lore.kernel.org/r/20220919143340.4527-2-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
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#
487d828d |
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26-Sep-2022 |
Ira Weiny <ira.weiny@intel.com> |
cxl/doe: Request exclusive DOE access The PCIE Data Object Exchange (DOE) mailbox is a protocol run over configuration cycles. It assumes one initiator at a time. While the kernel has control of the mailbox user space writes could interfere with the kernel access. Mark DOE mailbox config space exclusive when iterated by the CXL driver. Signed-off-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20220926215711.2893286-3-ira.weiny@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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#
9d24322e |
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19-Jul-2022 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
PCI/DOE: Add DOE mailbox support functions Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based mailbox with standard protocol discovery. Each mailbox is accessed through a DOE Extended Capability. Each DOE mailbox must support the DOE discovery protocol in addition to any number of additional protocols. Define core PCIe functionality to manage a single PCIe DOE mailbox at a defined config space offset. Functionality includes iterating, creating, query of supported protocol, and task submission. Destruction of the mailboxes is device managed. Cc: "Li, Ming" <ming4.li@intel.com> Cc: Bjorn Helgaas <helgaas@kernel.org> Cc: Matthew Wilcox <willy@infradead.org> Acked-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Co-developed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/20220719205249.566684-4-ira.weiny@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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#
e8e7fbb6 |
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12-Apr-2022 |
Pali Rohár <pali@kernel.org> |
PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro Add macro defining Auto Slot Power Limit Disable bit in Slot Control Register. Link: https://lore.kernel.org/r/20220412094946.27069-2-pali@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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#
fb82437f |
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18-Nov-2021 |
Baruch Siach <baruch@tkos.co.il> |
PCI: Change capability register offsets to hex Convert offsets of capability registers from decimal to hex. This matches the spec documents and is less error prone. [bhelgaas: also convert other capabilities with offsets > 8] Suggested-by: Bjorn Helgaas <helgaas@kernel.org> Link: https://lore.kernel.org/r/20210825160516.GA3576414@bjorn-Precision-5520/ Link: https://lore.kernel.org/r/aa067278adacbb59a675366052714081f4980f26.1637244780.git.baruch@tkos.co.il Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
80b3485f |
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07-Dec-2021 |
David E. Box <david.e.box@linux.intel.com> |
PCI: Add #defines for accessing PCIe DVSEC fields Add #defines for accessing Vendor ID, Revision, Length, and ID offsets in the Designated Vendor Specific Extended Capability (DVSEC). Defined in PCIe r5.0, sec 7.9.6. Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: David E. Box <david.e.box@linux.intel.com> Link: https://lore.kernel.org/r/20211208015015.891275-2-david.e.box@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
460275f1 |
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05-Oct-2021 |
Pali Rohár <pali@kernel.org> |
PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros Define a macro PCI_EXP_DEVCTL_PAYLOAD_* for every possible Max Payload Size in linux/pci_regs.h, in the same style as PCI_EXP_DEVCTL_READRQ_*. Link: https://lore.kernel.org/r/20211005180952.6812-2-kabel@kernel.org Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Marek Behún <kabel@kernel.org> Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
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#
c9d659b6 |
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20-Nov-2020 |
Qiuxu Zhuo <qiuxu.zhuo@intel.com> |
PCI/ERR: Bind RCEC devices to the Root Port driver If a Root Complex Integrated Endpoint (RCiEP) is implemented, it may signal errors through a Root Complex Event Collector (RCEC). Each RCiEP must be associated with no more than one RCEC. For an RCEC (which is technically not a Bridge), error messages "received" from associated RCiEPs must be enabled for "transmission" in order to cause a System Error via the Root Control register or (when the Advanced Error Reporting Capability is present) reporting via the Root Error Command register and logging in the Root Error Status register and Error Source Identification register. Given the commonality with Root Ports and the need to also support AER and PME services for RCECs, extend the Root Port driver to support RCEC devices by adding the RCEC Class ID to the driver structure. Co-developed-by: Sean V Kelley <sean.v.kelley@intel.com> Link: https://lore.kernel.org/r/20201121001036.8560-3-sean.v.kelley@intel.com Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
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#
34191749 |
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18-Nov-2020 |
Gustavo Pimentel <Gustavo.Pimentel@synopsys.com> |
PCI: Decode PCIe 64 GT/s link speed PCIe r6.0, sec 7.5.3.18, defines a new 64.0 GT/s bit in the Supported Link Speeds Vector of Link Capabilities 2. This patch does not affect the speed of the link, which should be negotiated automatically by the hardware; it only adds decoding when showing the speed to the user. Decode this new speed. Previously, reading the speed of a link operating at this speed showed "Unknown speed" instead of "64.0 GT/s". Link: https://lore.kernel.org/r/aaaab33fe18975e123a84aebce2adb85f44e2bbe.1605739760.git.gustavo.pimentel@synopsys.com Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
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#
1dc2da5c |
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28-Oct-2020 |
David E. Box <david.e.box@linux.intel.com> |
PCI: Add defines for Designated Vendor-Specific Extended Capability Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines for the header offsets. Defined in PCIe r5.0, sec 7.9.6. Signed-off-by: David E. Box <david.e.box@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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#
df8f1058 |
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15-Oct-2020 |
Saheed O. Bolarinwa <refactormyself@gmail.com> |
PCI/ASPM: Remove struct pcie_link_state.l1ss Previously we computed L1.2 parameters in the enumeration path, saved them in struct pcie_link_state.l1ss, and programmed them into the devices whenever we enabled or disabled L1.2 on the link. But these parameters are constant and don't need to be updated when enabling/disabling L1.2. Compute and program the L1.2 parameters once during enumeration and remove the struct pcie_link_state.l1ss member. No functional change intended. [bhelgaas: rework to program L1.2 parameters during enumeration] Link: https://lore.kernel.org/r/20201015193039.12585-13-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
c6e5f02b |
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15-Oct-2020 |
Saheed O. Bolarinwa <refactormyself@gmail.com> |
PCI/ASPM: Remove struct aspm_register_info.support Previously we stored the "ASPM Support" field from the Link Capabilities register in the struct aspm_register_info. Read the Link Capabilities directly when needed and remove it from the struct aspm_register_info. No functional change intended. [bhelgaas: remove pci_dev cached copy since LNKCAP isn't truly read-only, add PCI_EXP_LNKCAP_ASPM_L0S & PCI_EXP_LNKCAP_ASPM_L1, check them directly instead of adding aspm_support()] Link: https://lore.kernel.org/r/20201015193039.12585-5-helgaas@kernel.org Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
3789af9a |
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30-Jul-2020 |
Krzysztof Wilczyński <kw@linux.com> |
PCI/PM: Rename pci_dev.d3_delay to d3hot_delay PCI devices support two variants of the D3 power state: D3hot (main power present) D3cold (main power removed). Previously struct pci_dev contained: unsigned int d3_delay; /* D3->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ "d3_delay" refers specifically to the D3hot state. Rename it to "d3hot_delay" to avoid ambiguity and align with the ACPI "_DSM for Specifying Device Readiness Durations" in the PCI Firmware spec r3.2, sec 4.6.9. There is no change to the functionality. Link: https://lore.kernel.org/r/20200730210848.1578826-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
16270a92 |
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18-Aug-2020 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
PCI: designware-ep: Fix the Header Type check The current check will result in the multiple function device fails to initialize. So fix the check by masking out the multiple function bit. Link: https://lore.kernel.org/r/20200818092746.24366-1-Zhiqiang.Hou@nxp.com Fixes: 0b24134f7888 ("PCI: dwc: Add validation that PCIe core is set to correct mode") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
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#
20285359 |
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25-Oct-2019 |
Alexandru Gagniuc <mr.nuke.me@gmail.com> |
PCI: pciehp: Disable in-band presence detect when possible The presence detect state (PDS) is normally a logical OR of in-band and out-of-band (OOB) presence detect. As of PCIe 4.0, there is the option to disable in-band presence so that the PDS bit always reflects the state of the out-of-band presence. The recommendation of the PCIe spec is to disable in-band presence whenever supported (PCIe r5.0, appendix I implementation note): Due to architectural issues, the in-band (Physical-Layer-based) portion of the PD mechanism is deprecated for use with async hot-plug. One issue is that in-band PD as architected does not detect adapter removal during certain LTSSM states, notably the L1 and Disabled States. Another issue is that when both in-band and OOB PD are being used together, the Presence Detect State bit and its associated interrupt mechanism always reflect the logical OR of the inband and OOB PD states, and with some hot-plug hardware configurations, it is important for software to detect and respond to in-band and OOB PD events independently. If OOB PD is being used and the associated DSP supports In-Band PD Disable, it is recommended that the In-Band PD Disable bit be Set, and the Presence Detect State bit and its associated interrupt mechanism be used exclusively for OOB PD. As a substitute for in-band PD with async hot-plug, the reference model uses either the DPC or the DLL Link Active mechanism. Link: https://lore.kernel.org/r/20191025190047.38130-2-stuart.w.hayes@gmail.com [bhelgaas: move PCI_EXP_SLTCAP2 read earlier & print PCI_EXP_SLTCAP2_IBPD value (suggested by Lukas)] Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Lukas Wunner <lukas@wunner.de>
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#
ed22aaae |
|
08-Dec-2019 |
Dilip Kota <eswara.kota@linux.intel.com> |
PCI: dwc: intel: PCIe RC controller driver Add support to PCIe RC controller on Intel Gateway SoCs. PCIe controller is based of Synopsys DesignWare PCIe core. Intel PCIe driver requires Upconfigure support, Fast Training Sequence and link speed configurations. So adding the respective helper functions in the PCIe DesignWare framework. It also programs hardware autonomous speed during speed configuration so defining it in pci_regs.h. Also, mark Intel PCIe driver depends on MSI IRQ Domain as Synopsys DesignWare framework depends on the PCI_MSI_IRQ_DOMAIN. Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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#
bbdb2f5e |
|
12-Nov-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add #defines for Enter Compliance, Transmit Margin Add definitions for the Enter Compliance and Transmit Margin fields of the PCIe Link Control 2 register. Link: https://lore.kernel.org/r/20191112173503.176611-2-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
c9c13ba4 |
|
27-Sep-2019 |
Denis Efremov <efremov@linux.com> |
PCI: Add PCI_STD_NUM_BARS for the number of standard BARs Code that iterates over all standard PCI BARs typically uses PCI_STD_RESOURCE_END. However, that requires the unusual test "i <= PCI_STD_RESOURCE_END" rather than something the typical "i < PCI_STD_NUM_BARS". Add a definition for PCI_STD_NUM_BARS and change loops to use the more idiomatic C style to help avoid fencepost errors. Link: https://lore.kernel.org/r/20190927234026.23342-1-efremov@linux.com Link: https://lore.kernel.org/r/20190927234308.23935-1-efremov@linux.com Link: https://lore.kernel.org/r/20190916204158.6889-3-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sebastian Ott <sebott@linux.ibm.com> # arch/s390/ Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> # video/fbdev/ Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> # pci/controller/dwc/ Acked-by: Jack Wang <jinpu.wang@cloud.ionos.com> # scsi/pm8001/ Acked-by: Martin K. Petersen <martin.petersen@oracle.com> # scsi/pm8001/ Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # memstick/
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#
106feb2f |
|
03-Sep-2019 |
Denis Efremov <efremov@linux.com> |
PCI: pciehp: Remove pciehp_set_attention_status() Remove pciehp_set_attention_status() and use pciehp_set_indicators() instead, since the code is mostly the same. Link: https://lore.kernel.org/r/20190903111021.1559-4-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
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#
448d5a55 |
|
13-Aug-2019 |
Vidya Sagar <vidyas@nvidia.com> |
PCI: Add #defines for some of PCIe spec r4.0 features Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and sec 7.7.5 for Physical Layer 16.0 GT/s. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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#
de76cda2 |
|
04-Jun-2019 |
Gustavo Pimentel <Gustavo.Pimentel@synopsys.com> |
PCI: Decode PCIe 32 GT/s link speed PCIe r5.0, sec 7.5.3.18, defines a new 32.0 GT/s bit in the Supported Link Speeds Vector of Link Capabilities 2. Decode this new speed. This does not affect the speed of the link, which should be negotiated automatically by the hardware; it only adds decoding when showing the speed to the user. Previously, reading the speed of a link operating at this speed showed "Unknown speed" instead of "32.0 GT/s". Link: https://lore.kernel.org/lkml/92365e3caf0fc559f9ab14bcd053bfc92d4f661c.1559664969.git.gustavo.pimentel@synopsys.com Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
2dbce590 |
|
19-Nov-2018 |
Subbaraya Sundeep <sbhatta@marvell.com> |
PCI: Assign bus numbers present in EA capability for bridges The "Enhanced Allocation (EA) for Memory and I/O Resources" ECN, approved 23 October 2014, sec 6.9.1.2, specifies a second DW in the capability for type 1 (bridge) functions to describe fixed secondary and subordinate bus numbers. This ECN was included in the PCIe r4.0 spec, but sec 6.9.1.2 was omitted, presumably by mistake. Read fixed bus numbers from the EA capability for bridges. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> [bhelgaas: add pci_ea_fixed_busnrs() return value] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
35d0a06d |
|
04-Feb-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Cleanup register definition width and whitespace Follow the file conventions of: - register offsets not indented - fields within a register indented one space - field masks use same width as register - register field values indented an additional space No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
8c938ddc |
|
19-Feb-2019 |
Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> |
PCI/ATS: Add pci_ats_page_aligned() interface Return the Page Aligned Request bit in the ATS Capability Register. As per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit is set, it indicates the Untranslated Addresses generated by the device are always aligned to a 4096 byte boundary. An IOMMU that can only translate page-aligned addresses can only be used with devices that always produce aligned Untranslated Addresses. This interface will be used by drivers for such IOMMUs to determine whether devices can use the ATS service. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Keith Busch <keith.busch@intel.com> Suggested-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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#
e5567f5f |
|
19-Feb-2019 |
Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> |
PCI/ATS: Add pci_prg_resp_pasid_required() interface. Return the PRG Response PASID Required bit in the Page Request Status Register. As per PCIe spec r4.0, sec 10.5.2.3, if this bit is Set, the device expects a PASID TLP Prefix on PRG Response Messages when the corresponding Page Requests had a PASID TLP Prefix. If Clear, the device does not expect PASID TLP Prefixes on any PRG Response Message, and the device behavior is undefined if the device receives a PRG Response Message with a PASID TLP Prefix. Also the device behavior is undefined if this bit is Set and the device receives a PRG Response Message with no PASID TLP Prefix when the corresponding Page Requests had a PASID TLP Prefix. This function will be used by drivers like IOMMU, if it is required to check the status of the PRG Response PASID Required bit before enabling the PASID support of the device. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Keith Busch <keith.busch@intel.com> Suggested-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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#
d6112f8d |
|
07-Sep-2018 |
Felipe Balbi <felipe.balbi@linux.intel.com> |
PCI: Add support for Immediate Readiness PCIe r4.0, sec 7.5.1.1.4 defines a new bit in the Status Register: Immediate Readiness – This optional bit, when Set, indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration Requests to this Function. When this bit is Set, for accesses to this Function, software is exempt from all requirements to delay configuration accesses following any type of reset, including but not limited to the timing requirements defined in Section 6.6. This means that all delays after a Conventional or Function Reset can be skipped. This patch reads such bit and caches its value in a flag inside struct pci_dev to be checked later if we should delay or can skip delays after a reset. While at that, also move the explicit msleep(100) call from pcie_flr() and pci_af_flr() to pci_dev_wait(). Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> [bhelgaas: rename PCI_STATUS_IMMEDIATE to PCI_STATUS_IMM_READY] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
7ce3f912 |
|
30-Jun-2018 |
Sinan Kaya <okaya@codeaurora.org> |
PCI: Enable PASID only if entire path supports End-End TLP prefixes A PCIe endpoint carries the process address space identifier (PASID) in the TLP prefix as part of the memory read/write transaction. The address information in the TLP is relevant only for a given PASID context. An IOMMU takes PASID value and the address information from the TLP to look up the physical address in the system. PASID is an End-End TLP Prefix (PCIe r4.0, sec 6.20). Sec 2.2.10.2 says It is an error to receive a TLP with an End-End TLP Prefix by a Receiver that does not support End-End TLP Prefixes. A TLP in violation of this rule is handled as a Malformed TLP. This is a reported error associated with the Receiving Port (see Section 6.2). Prevent error condition by proactively requiring End-End TLP prefix to be supported on the entire data path between the endpoint and the root port before enabling PASID. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
b1277a22 |
|
29-Jun-2018 |
Christian König <ckoenig.leichtzumerken@gmail.com> |
PCI: Cleanup PCI_REBAR_CTRL_BAR_SHIFT handling Cleanup PCI_REBAR_CTRL_BAR_SHIFT handling. That was hard coded instead of properly defined in the header for some reason. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
6927868e |
|
17-May-2018 |
Oza Pawandeep <poza@codeaurora.org> |
PCI/DPC: Disable ERR_NONFATAL handling by DPC PCIe ERR_NONFATAL errors mean a particular transaction is unreliable but the Link is otherwise fully functional (PCIe r4.0, sec 6.2.2). The AER driver handles these by logging the error details and calling driver-supplied pci_error_handlers callbacks. It does not reset downstream devices, does not remove them from the PCI subsystem, does not re-enumerate them, and does not call their driver .remove() or .probe() methods. But DPC driver previously enabled DPC on ERR_NONFATAL, so if the hardware supports DPC, these errors caused a Link reset (performed automatically by the hardware), followed by the DPC driver removing affected devices (which calls their .remove() methods), bringing the Link back up, and re-enumerating (which calls driver .probe() methods). Disable ERR_NONFATAL DPC triggering so these errors will only be handled by AER. This means drivers won't have to deal with different usage of their pci_error_handlers callbacks and .probe() and .remove() methods based on whether the platform has DPC support. Signed-off-by: Oza Pawandeep <poza@codeaurora.org> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
c80851f6 |
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16-Apr-2018 |
Frederick Lawler <fred@fredlawl.com> |
PCI: Add PCI_EXP_LNKCTL2_TLS* macros The Link Control 2 register is missing macros for Target Link Speeds. Add those in. Signed-off-by: Frederick Lawler <fred@fredlawl.com> [bhelgaas: use "GT" instead of "GB"] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
a5724fc3 |
|
16-Apr-2018 |
Heiner Kallweit <hkallweit1@gmail.com> |
PCI: Add two more values for PCIe Max_Read_Request_Size This patch adds missing values for the max read request size. E.g. network driver r8169 uses a value of 4K. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
1acfb9b7 |
|
12-Mar-2018 |
Jay Fang <f.fangjian@huawei.com> |
PCI: Add decoding for 16 GT/s link speed PCIe 4.0 defines the 16.0 GT/s link speed. Links can run at that speed without any Linux changes, but previously their sysfs "max_link_speed" and "current_link_speed" files contained "Unknown speed", not the expected "16.0 GT/s". Add decoding for the new 16 GT/s link speed. Signed-off-by: Jay Fang <f.fangjian@huawei.com> [bhelgaas: add PCI_EXP_LNKCAP2_SLS_16_0GB] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Dongdong Liu <liudongdong3@huawei.com>
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#
65d5e913 |
|
16-Jan-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/DPC: Reformat DPC register definitions Reformat DPC register definitions to follow the convention that register field masks indicate the register width, e.g., a field of a 16-bit register uses a mask of 4 hex digits, with leading zeros included as needed. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com> Reviewed-by: Sinan Kaya <okaya@codeaurora.org>
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#
01060e3d |
|
16-Jan-2018 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/DPC: Add and use DPC Status register field definitions Add definitions for DPC Status register fields and use them in the code. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com> Reviewed-by: Sinan Kaya <okaya@codeaurora.org>
|
#
430a2368 |
|
04-Jan-2018 |
Jay Cornwall <Jay.Cornwall@amd.com> |
PCI: Add pci_enable_atomic_ops_to_root() The Atomic Operations feature (PCIe r4.0, sec 6.15) allows atomic transctions to be requested by, routed through and completed by PCIe components. Routing and completion do not require software support. Component support for each is detectable via the DEVCAP2 register. A Requester may use AtomicOps only if its PCI_EXP_DEVCTL2_ATOMIC_REQ is set. This should be set only if the Completer and all intermediate routing elements support AtomicOps. A concrete example is the AMD Fiji-class GPU (which is capable of making AtomicOp requests), below a PLX 8747 switch (advertising AtomicOp routing) with a Haswell host bridge (advertising AtomicOp completion support). Add pci_enable_atomic_ops_to_root() for per-device control over AtomicOp requests. This checks to be sure the Root Port supports completion of the desired AtomicOp sizes and the path to the Root Port supports routing the AtomicOps. Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> [bhelgaas: changelog, comments, whitespace] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
fdabc3fe |
|
15-Dec-2017 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add #defines for Completion Timeout Disable feature Add #defines for the Completion Timeout Disable feature and use them. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michael Ellerman <mpe@ellerman.id.au>
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#
a48f3d5b |
|
13-Nov-2017 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/ASPM: Add L1 Substates definitions Add and use #defines for L1 Substate register fields instead of hard-coding the masks. Also update comments to use names from the spec. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
|
#
7f88ba4a |
|
10-Nov-2017 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/ASPM: Reformat ASPM register definitions Reformat register field definitions in the style used elsewhere and align comments with names used in the spec. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
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#
6f52b16c |
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01-Nov-2017 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
License cleanup: add SPDX license identifier to uapi header files with no license Many user space API headers are missing licensing information, which makes it hard for compliance tools to determine the correct license. By default are files without license information under the default license of the kernel, which is GPLV2. Marking them GPLV2 would exclude them from being included in non GPLV2 code, which is obviously not intended. The user space API headers fall under the syscall exception which is in the kernels COPYING file: NOTE! This copyright does *not* cover user programs that use kernel services by normal system calls - this is merely considered normal use of the kernel, and does *not* fall under the heading of "derived work". otherwise syscall usage would not be possible. Update the files which contain no license information with an SPDX license identifier. The chosen identifier is 'GPL-2.0 WITH Linux-syscall-note' which is the officially assigned identifier for the Linux syscall exception. SPDX license identifiers are a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. See the previous patch in this series for the methodology of how this patch was researched. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
276b738d |
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24-Oct-2017 |
Christian König <christian.koenig@amd.com> |
PCI: Add resizable BAR infrastructure Add resizable BAR infrastructure, including defines and helper functions to read the possible sizes of a BAR and update its size. See PCIe r3.1, sec 7.22. Link: https://pcisig.com/sites/default/files/specification_documents/ECN_Resizable-BAR_24Apr2008.pdf Signed-off-by: Christian König <christian.koenig@amd.com> [bhelgaas: rename to functions with "rebar" (to match #defines), drop shift #defines, drop "_MASK" suffixes, fix typos, fix kerneldoc] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
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#
7c950b9e |
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11-Oct-2017 |
Dongdong Liu <liudongdong3@huawei.com> |
PCI/portdrv: Add #defines for AER and DPC Interrupt Message Number masks In the AER case, the mask isn't strictly necessary because there are no higher-order bits above the Interrupt Message Number, but using a #define will make it possible to grep for it. Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
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#
8fc614c0 |
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31-Aug-2017 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI/AER: Reformat AER register definitions Reformat so comments fit on same line as definition. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
f20c4ea4 |
|
19-Aug-2017 |
Dongdong Liu <liudongdong3@huawei.com> |
PCI/DPC: Add eDPC support Add eDPC support. Get and print the RP PIO error information when the trigger condition is RP PIO error. For more information on eDPC, please see PCI Express Base Specification Revision 3.1, section 6.2.10.3, or view the PCI-SIG eDPC ECN here: https://pcisig.com/sites/default/files/specification_documents/ECN_Enhanced_DPC_2012-11-19_final.pdf Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com>
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#
ea5311c7 |
|
10-Aug-2017 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Fix PCIe capability sizes PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 defines the size of the PCIe capability structure for v1 devices with link, but we also have a need in the vfio code for sizing the capability for devices without link, such as Root Complex Integrated Endpoints. Create a separate define for this ending the structure before the link fields. Additionally, this reveals that PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 is currently incorrect, ending the capability length before the v2 link fields. Rename this to specify an RC Integrated Endpoint (no link) capability length and move PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 to include the link fields as we have for the v1 version. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> [bhelgaas: add "_" in "PCI_CAP_EXP_RC ENDPOINT_SIZEOF_V2 44"] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com>
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#
56c1af46 |
|
01-Jun-2017 |
Wong Vee Khee <vee.khee.wong@ni.com> |
PCI: Add sysfs max_link_speed/width, current_link_speed/width, etc Expose PCIe bridges attributes such as secondary bus number, subordinate bus number, max link speed and link width, current link speed and link width via sysfs in /sys/bus/pci/devices/... This information is available via lspci, but that requires root privilege. Signed-off-by: Wong Vee Khee <vee.khee.wong@ni.com> Signed-off-by: Hui Chun Ong <hui.chun.ong@ni.com> [bhelgaas: changelog, return errors early to unindent usual case, return errors with same style throughout] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
f92faaba |
|
27-Apr-2017 |
Amrani, Ram <Ram.Amrani@cavium.com> |
RDMA/qedr: properly check atomic capabilities After checking the path upwards towards root complex, actualy check root complex atomic_req capability, and not our own NIC. Verify that the PCIe device control register's atomic egress block is cleared in the path. Verify that the PCIe version is at least 2. Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
76dc5268 |
|
14-Apr-2017 |
Matthias Kaehlcke <mka@chromium.org> |
PCI: Make PCI_ROM_ADDRESS_MASK a 32-bit constant A 64-bit value is not needed since a PCI ROM address consists in 32 bits. This fixes a clang warning about "implicit conversion from 'unsigned long' to 'u32'". Also remove now unnecessary casts to u32 from __pci_read_base() and pci_std_update_resource(). Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
0fc1223f |
|
02-Jan-2017 |
Rajat Jain <rajatja@google.com> |
PCI/ASPM: Add L1 substate capability structure register definitions Add L1 substate capability structure register definitions for use in subsequent patches. See the PCIe r3.1 spec, sec 7.33. [bhelgaas: add PCIe spec reference] Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
abdbf4d6 |
|
03-Feb-2017 |
Keith Busch <kbusch@kernel.org> |
PCI/DPC: Wait for Root Port busy to clear Per PCIe r3.1, sec 6.2.10 and sec 7.13.4, on Root Ports that support "RP Extensions for DPC", When the DPC Trigger Status bit is Set and the DPC RP Busy bit is Set, software must leave the Root Port in DPC until the DPC RP Busy bit reads 0b. Wait up to 1 second for the Root Port to become non-busy. [bhelgaas: changelog, spec references] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
cc10385b |
|
21-Sep-2016 |
Wang Sheng-Hui <shhuiw@foxmail.com> |
PCI: Move config space size macros to pci_regs.h Move PCI configuration space size macros (PCI_CFG_SPACE_SIZE and PCI_CFG_SPACE_EXP_SIZE) from drivers/pci/pci.h to include/uapi/linux/pci_regs.h so they can be used by more drivers and eliminate duplicate definitions. [bhelgaas: Expand comment to include PCI-X details] Signed-off-by: Wang Sheng-Hui <shhuiw@foxmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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#
2e0cbc4d |
|
10-Oct-2016 |
Ram Amrani <Ram.Amrani@cavium.com> |
qedr: Add RoCE driver framework Adds a skeletal implementation of the qed* RoCE driver - basically the ability to communicate with the qede driver and receive notifications from it regarding various init/exit events. Signed-off-by: Rajesh Borundia <rajesh.borundia@cavium.com> Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
|
#
8b2ec318 |
|
12-Jun-2016 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add PTM clock granularity information The PTM Control register (PCIe r3.1, sec 7.32.3) contains an Effective Granularity field: This provides information relating to the expected accuracy of the PTM clock, but does not otherwise affect the PTM mechanism. Set the Effective Granularity based on the PTM Root and any intervening PTM Time Sources. This does not set Effective Granularity for Root Complex Integrated Endpoints because I don't know how to figure out clock granularity for them. The spec says: ... system software must set [Effective Granularity] to the value reported in the Local Clock Granularity field by the associated PTM Time Source. but I don't know how to identify the associated PTM Time Source. Normally it's the upstream bridge, but an integrated endpoint has no upstream bridge. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
eec097d4 |
|
13-Jun-2016 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add pci_enable_ptm() for drivers to enable PTM on endpoints Add an pci_enable_ptm() interface so drivers can enable PTM. The PCI core enables PTM on PTM Roots and switches automatically, but we don't enable PTM on endpoints unless a driver requests it. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
9bb04a0c |
|
11-Jun-2016 |
Jonathan Yong <jonathan.yong@intel.com> |
PCI: Add Precision Time Measurement (PTM) support Add Precision Time Measurement (PTM) support (see PCIe r3.1, sec 6.22). Enable PTM on PTM Root devices and switch ports. This does not enable PTM on endpoints. There currently are no PTM-capable devices on the market, but it is expected to be supported by the Intel Apollo Lake platform. [bhelgaas: complete rework] Signed-off-by: Jonathan Yong <jonathan.yong@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
26e51571 |
|
28-Apr-2016 |
Keith Busch <kbusch@kernel.org> |
PCI: Add Downstream Port Containment driver Add driver for the PCI Express Downstream Port Containment extended capability. DPC is an optional capability to contain uncorrectable errors below a port. For more information on DPC, please see PCI Express Base Specification Revision 4, section 7.31, or view the PCI-SIG DPC ECN here: https://pcisig.com/sites/default/files/specification_documents/ECN_DPC_2012-02-09_finalized.pdf When a DPC event is triggered, the hardware disables downstream links, so the DPC driver schedules removal for all devices below this port. This may happen concurrently with a PCIe hotplug driver if enabled. When all downstream devices are removed and the link state transitions to disabled, the DPC driver clears the DPC status and interrupt bits so the link may retrain for a newly connected device. [bhelgaas: clear (not set) DPC_CTL bits on remove, whitespace cleanup] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lukas Wunner <lukas@wunner.de>
|
#
10126ac1 |
|
02-May-2016 |
Keith Busch <kbusch@kernel.org> |
PCI: Add Downstream Port Containment portdrv service type Add the Downstream Port Containment (PCIE_PORT_SERVICE_DPC) portdrv service type, available if the device has the DPC extended capability. [bhelgaas: split to separate patch, changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
26635112 |
|
29-Oct-2015 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Make Enhanced Allocation bitmasks more obvious Expand bitmask #defines completely. This puts the shift in the code instead of in the #define, but it makes it more obvious in the header file how fields in the register are laid out. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
#
f80b0ba9 |
|
29-Oct-2015 |
Sean O. Stalley <sean.stalley@intel.com> |
PCI: Add Enhanced Allocation register entries Add registers defined in PCI-SIG's Enhanced allocation ECN. [bhelgaas: s/WRITEABLE/WRITABLE] Signed-off-by: Sean O. Stalley <sean.stalley@intel.com> [david.daney@cavium.com: Added more definitions for PCI_EA_BEI_*] Signed-off-by: Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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c9ddbac9 |
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14-Jul-2015 |
Michael S. Tsirkin <mst@redhat.com> |
PCI: Restore PCI_MSIX_FLAGS_BIRMASK definition 09a2c73ddfc7 ("PCI: Remove unused PCI_MSIX_FLAGS_BIRMASK definition") removed PCI_MSIX_FLAGS_BIRMASK from an exported header because it was unused in the kernel. But that breaks user programs that were using it (QEMU in particular). Restore the PCI_MSIX_FLAGS_BIRMASK definition. [bhelgaas: changelog] Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.13+
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5929b8a3 |
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26-Jan-2015 |
Rafał Miłecki <zajec5@gmail.com> |
PCI: Add defines for PCIe Max_Read_Request_Size There are a few drivers using magic numbers when operating with PCIe capabilities and PCI_EXP_DEVCTL_READRQ. Define known values to allow cleaning their code a bit. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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846fc709 |
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13-Aug-2014 |
Chen, Gong <gong.chen@linux.intel.com> |
PCI/AER: Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND In PCIe r1.0, sec 5.10.2, bit 0 of the Uncorrectable Error Status, Mask, and Severity Registers was for "Training Error." In PCIe r1.1, sec 7.10.2, bit 0 was redefined to be "Undefined." Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND to reflect this change. No functional change. [bhelgaas: changelog] Signed-off-by: Chen, Gong <gong.chen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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f3dbd802 |
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02-Sep-2014 |
Rajat Jain <rajatxjain@gmail.com> |
PCI: Enable CRS Software Visibility for root port if it is supported Per PCIe r3.0, sec 2.3.2, an endpoint may respond to a Configuration Request with a Completion with Configuration Request Retry Status (CRS). This terminates the Configuration Request. When the CRS Software Visibility feature is disabled (as it is by default), a Root Complex must handle a CRS Completion by re-issuing the Configuration Request. This is invisible to software. From the CPU's point of view, an endpoint that always responds with CRS causes a hang because the Root Complex never supplies data to complete the CPU read. When CRS Software Visibility is enabled, a Root Complex that receives a CRS Completion for a read of the Vendor ID must return data of 0x0001. The Vendor ID of 0x0001 indicates to software that the endpoint is not ready. We now have more devices that require CRS Software Visibility. For example, a PLX 8713 NT bridge may respond with CRS until it has been configured via I2C, and the I2C configuration is completely independent of PCI enumeration. Enable CRS Software Visibility if it is supported. This allows a system with such a device to work (though the PCI core times out waiting for it to become ready, and we have to rescan the bus after it is ready). This essentially reverts ad7edfe04908 ("[PCI] Do not enable CRS Software Visibility by default"). The failures that led to ad7edfe04908 should be addressed by 89665a6a7140 ("PCI: Check only the Vendor ID to identify Configuration Request Retry"). [bhelgaas: changelog] Link: http://lkml.kernel.org/r/20071029061532.5d10dfc6@snowcone Link: http://lkml.kernel.org/r/alpine.LFD.0.9999.0712271023090.21557@woody.linux-foundation.org Signed-off-by: Rajat Jain <rajatxjain@gmail.com> Signed-off-by: Rajat Jain <rajatjain@juniper.net> Signed-off-by: Guenter Roeck <groeck@juniper.net> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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55fdbfe7 |
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28-Dec-2013 |
Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
pci_regs.h: Add PCI bus link speed and width defines Add missing PCI bus link speed 8.0 GT/s and bus link widths of x1, x2, x4 and x8. CC: <linux-kernel@vger.kernel.org> CC: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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274127a1 |
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17-Dec-2013 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Rename PCI_VC_PORT_REG1/2 to PCI_VC_PORT_CAP1/2 These are set of two capability registers, it's pretty much given that they're registers, so reflect their purpose in the name. Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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425c1b22 |
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17-Dec-2013 |
Alex Williamson <alex.williamson@redhat.com> |
PCI: Add Virtual Channel to save/restore support While we don't really have any infrastructure for making use of VC support, the system BIOS can configure the topology to non-default VC values prior to boot. This may be due to silicon bugs, desire to reserve traffic classes, or perhaps just BIOS bugs. When we reset devices, the VC configuration may return to default values, which can be incompatible with devices upstream. For instance, Nvidia GRID cards provide a PCIe switch and some number of GPUs, all supporting VC. The power-on default for VC is to support TC0-7 across VC0, however some platforms will only enable TC0/VC0 mapping across the topology. When we do a secondary bus reset on the downstream switch port, the GPU is reset to a TC0-7/VC0 mapping while the opposite end of the link only enables TC0/VC0. If the GPU attempts to use TC1-7, it fails. This patch attempts to provide complete support for VC save/restore, even beyond the minimally required use case above. This includes save/restore and reload of the arbitration table, save/restore and reload of the port arbitration tables, and re-enabling of the channels for VC, VC9, and MFVC capabilities. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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e7b4f0d7 |
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14-Dec-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: pciehp: Use symbolic constants for Slot Control fields Add symbolic constants for the PCIe Slot Control indicator and power control fields defined by spec and use them instead of open-coded hex constants. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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f7625980 |
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14-Nov-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Fix whitespace, capitalization, and spelling errors Fix whitespace, capitalization, and spelling errors. No functional change. I know "busses" is not an error, but "buses" was more common, so I used it consistently. Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus()) Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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09a2c73d |
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12-Sep-2013 |
Yijing Wang <wangyijing@huawei.com> |
PCI: Remove unused PCI_MSIX_FLAGS_BIRMASK definition PCI_MSIX_FLAGS_BIRMASK has been replaced by PCI_MSIX_TABLE_BIR for better readability. Now no one uses it, remove it. No functional change. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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ad4d35f8 |
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05-Sep-2013 |
Yijing Wang <wangyijing@huawei.com> |
[SCSI] csiostor: Use pcie_capability_clear_and_set_word() to simplify code pci_is_pcie() and pcie_capability_clear_and_set_word() make it trivial to set the PCIe Completion Timeout, so just fold the csio_set_pcie_completion_timeout() function into its caller. [bhelgaas: changelog, fold csio_set_pcie_completion_timeout() into caller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@huawei.com> Cc: "James E.J. Bottomley" <JBottomley@parallels.com> Cc: Naresh Kumar Inna <naresh@chelsio.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jesper Juhl <jj@chaosbits.net>
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bd6fb762 |
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27-Aug-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add offsets of PCIe capability registers These offsets are not used, and in some cases are completely reserved even in the spec, but I'm adding them for completeness just to match the diagrams in the spec, e.g., PCIe spec r3.0, sec 7.8. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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c0b4b381 |
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27-Aug-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Tidy bitmasks and spacing of PCIe capability definitions The convention of showing bits in a mask of the full register width, e.g., "0x00000007" instead of "0x07" for a field in a 32-bit register, is common but not universal in this file. This patch makes it consistently used at least for the PCIe capability. Whitespace and zero-extension changes only; no functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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1b121c24 |
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27-Aug-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Remove obsolete comment reference to pci_pcie_cap2() pci_pcie_cap2() was replaced by pcie_capability_read_word() and similar functions, so update the comment. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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fbf501c3 |
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27-Aug-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment The PCI_EXP_TYPE_PCI_BRIDGE is a *PCIe* function that is a bridge to PCI/PCI-X. See PCIe spec r3.0, sec 7.8.2. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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d2ab1fa6 |
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27-Aug-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Rename PCIe capability definitions to follow convention All other PCIe capability register fields include "PCI_EXP" + <reg-name> + <field-name>. This renames PCI_EXP_OBFF_MASK, PCI_EXP_IDO_REQ_EN, PCI_EXP_LTR_EN, and related fields using the same convention. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Samuel Ortiz <sameo@linux.intel.com> # for MFD driver
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cb93b186 |
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29-May-2013 |
Yijing Wang <wangyijing@huawei.com> |
PCI: Fix comment typo for PCI_EXP_LNKCAP_CLKPM Fix trivial typo for PCI_EXP_LNKCAP_CLKPM comment. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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24bc69da |
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17-Apr-2013 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Clean up MSI/MSI-X capability #defines This doesn't change any existing symbols, but it puts them in logical order and uses explicit masks instead of shifts, like the rest of the file. It also adds new symbols for PCI_MSIX_TABLE_BIR, PCI_MSIX_TABLE_OFFSET, PCI_MSIX_PBA_BIR, and PCI_MSIX_PBA_OFFSET to replace the mis-named PCI_MSIX_FLAGS_BIRMASK (the BAR index fields are part of the Table and PBA registers, not the flags register). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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130f1b8f |
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26-Dec-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add PCIe Link Capability link speed and width names Add standard #defines for the Supported Link Speeds field in the PCIe Link Capabilities register. Note that prior to PCIe spec r3.0, these encodings were defined: 0001b 2.5GT/s Link speed supported 0010b 5.0GT/s and 2.5GT/s Link speed supported Starting with spec r3.0, these encodings refer to bits 0 and 1 in the Supported Link Speeds Vector in the Link Capabilities 2 register, and bits 0 and 1 there mean 2.5 GT/s and 5.0 GT/s, respectively. Therefore, code that followed r2.0 and interpreted 0x1 as 2.5GT/s and 0x2 as 5.0GT/s will continue to work, and we can identify a device using the new encodings because it will have a non-zero Link Capabilities 2 register. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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75083206 |
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05-Dec-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add standard PCIe Capability Link ASPM field names Add standard #defines for ASPM fields in PCI Express Link Capability and Link Control registers. Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1 directly, but these are defined for the Linux ASPM interfaces, e.g., pci_disable_link_state(), and only coincidentally match the actual register bits. PCIE_LINK_STATE_CLKPM, also part of that interface, does not match the register bit. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Acked-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
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7793eeab |
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05-Dec-2012 |
Bjorn Helgaas <bhelgaas@google.com> |
PCI: Add and use standard PCI-X Capability register names Add and use #defines for PCI-X Capability registers and fields. Note that the PCI-X Capability has a different layout for type 0 (endpoint) and type 1 (bridge) devices. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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b891b4dc |
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08-Nov-2012 |
Jingoo Han <jg1.han@samsung.com> |
PCI: Fix bit definitions of PCI_EXP_LNKCAP2 register According to the PCIe 3.0 spec, PCI_EXP_LNKCAP2_SLS_2_5GB is 1st bit of PCI_EXP_LNKCAP2 register, not 0th bit. So, the bit definition of supported link speed vector should be fixed. [bhelgaas: change "Current" to "Supported"] Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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607ca46e |
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13-Oct-2012 |
David Howells <dhowells@redhat.com> |
UAPI: (Scripted) Disintegrate include/linux Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Michael Kerrisk <mtk.manpages@gmail.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
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