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8b78de95 |
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14-Dec-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: constify uniphier_pinctrl_socdata These are constant data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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34812fe1 |
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05-Dec-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: convert to SPDX License Identifier checkpatch.pl suggests to use SPDX license tag. I am happy to follow it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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e24cf513 |
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15-Oct-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h> The reason of including <linux/bitops.h> here is just for BIT() macro. Since commit 8bd9cb51daac8 ("locking/atomics, asm-generic: Move some macros from <linux/bitops.h> to a new <linux/bits.h> file"), <linux/bits.h> is enough for such compile-time macros. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6d363bd1 |
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02-Sep-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: include <linux/build_bug.h> instead of <linux/bug.h> The #includes <linux/bug.h> is here to use BUILD_BUG_ON_ZERO(). Thanks to commit bc6245e5efd7 ("bug: split BUILD_BUG stuff out into <linux/build_bug.h>"), it is now possible to reduce the number of headers pulled in. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9697509e |
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31-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: add suspend / resume support Save registers lost in the sleep when suspending, and restore them when resuming. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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4e767983 |
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31-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: omit redundant input enable bit information For LD11/20 SoCs (capable of per-pin input enable), the iectrl bit number matches its pin number. So, this is redundant information. Instead, we just need a flag to know if the iectrl gating exists or not. With this refactoring, 5 bits in pin data will be saved. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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7f6ee0a5 |
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31-Jul-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: clean up GPIO port muxing There are a bunch of GPIO muxing data, but most of them are actually unneeded because GPIO-to-pin mapping can be specified by "gpio-ranges" DT properties. Tables that contain a set of GPIO pins are still needed for the named mapping by "gpio-ranges-group-names". This is a much cleaner way for UniPhier SoC family where GPIO numbers are not straight mapped to pin numbers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8ef364b3 |
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15-Mar-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: remove obsoleted compatibles Since commit 3e030b0b4e46 ("pinctrl: uniphier: allow to have pinctrl node under syscon node"), this driver has kept compatibility for the old DT files. Several releases have passed since then, so remove the obsoleted compatibles and clean up the code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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39ec9ace |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: support pin configuration for dedicated pins PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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aa543888 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: support per-pin input enable for new SoCs Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit updates the core part for that. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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c2ebf475 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: introduce capability flag The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding the new one. Having just one flag would be better than adding a new struct member every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from a customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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72e5706a |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: support 3-bit drive strength control The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Drive strength of some pins are controlled by 3-bit width registers (8-level granularity). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9eaa98a6 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: rename macros for drive strength control The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Some of the configuration registers on it have 3-bit width. The feature will be supported in the next commit, but a problem is that macro names are getting longer and longer in the current naming scheme. Before moving forward, this commit renames macros as follows: UNIPHIER_PIN_DRV_4_8 -> UNIPHIER_PIN_DRV_1BIT UNIPHIER_PIN_DRV_8_12_16_20 -> UNIPHIER_PIN_DRV_2BIT UNIPHIER_PIN_DRV_FIXED_4 -> UNIPHIER_PIN_DRV_FIXED4 UNIPHIER_PIN_DRV_FIXED_5 -> UNIPHIER_PIN_DRV_FIXED5 UNIPHIER_PIN_DRV_FIXED_8 -> UNIPHIER_PIN_DRV_FIXED8 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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fc78a566 |
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31-May-2016 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: uniphier: allocate struct pinctrl_desc in probe function Currently, every SoC driver defines struct pinctrl_desc statically, i.e. it consumes memory footprint even if it is not probed. In multi-platform, many pinctrl drivers are linked (generally as built-in objects), although only one of them is actually used. So, it is reasonable to allocate memory dynamically where possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1ac471ed |
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24-Feb-2016 |
Laxman Dewangan <ldewangan@nvidia.com> |
pinctrl: uniphier: Use devm_pinctrl_register() for pinctrl registration Use devm_pinctrl_register() for pin control registration and remove need of .remove callback. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6e908892 |
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13-Jul-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: UniPhier: add UniPhier pinctrl core support The core support for the pinctrl drivers for all the UniPhier SoCs. Changes in v2: - drop vogus THIS_MODULE because this file is always built-in - drop vogus "include <linux/module.h> because this file is always built-in Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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