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068866fb |
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03-Oct-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Replace kernel.h by what is actually being used The kernel.h is a mess of unrelated things and we only used it as a proxy to array_size.h, hence switch from former to the latter. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
4e1edcc7 |
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13-Aug-2023 |
Raag Jadav <raag.jadav@intel.com> |
pinctrl: merrifield: Adapt to Intel Tangier driver Make use of Intel Tangier as a library driver for Merrifield. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Link: https://lore.kernel.org/r/20230814054033.12004-3-raag.jadav@intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
29cf9f36 |
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05-Jun-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Use BUFCFG_PINMODE_GPIO in ->pin_dbg_show() Use explicit comparison to BUFCFG_PINMODE_GPIO instead of implying it. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
9891422b |
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05-Jun-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Fix open-drain pin mode configuration Currently the pin may not be configured as open-drain in some cases because the argument may be 0 for the boolean types of the pin configurations. Fix this by ignoring the argument. With that, allow to actually restore pin to the push-pull mode. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
de82e6f0 |
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19-Dec-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Convert to use new memeber in struct intel_function Convert driver to use generic data type and hence a new member in the struct intel_function. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
3886bc35 |
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02-Nov-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Use temporary variable for struct device Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
cc994a0a |
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07-Oct-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
98c23f60 |
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20-Jun-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Switch to to embedded struct pingroup Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
03a61f11 |
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11-Nov-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Set default bias in case no particular value given When GPIO library asks pin control to set the bias, it doesn't pass any value of it and argument is considered boolean (and this is true for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual drivers must behave well, when they got the resistance value of 1 Ohm, i.e. transforming it to sane default. In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible because it gives a good trade off between weakness and minimization of leakage current (will be only 50 uA with the above choice). Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
0fa86fc2 |
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11-Nov-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Set default bias in case no particular value given When GPIO library asks pin control to set the bias, it doesn't pass any value of it and argument is considered boolean (and this is true for ACPI GpioIo() / GpioInt() resources, by the way). Thus, individual drivers must behave well, when they got the resistance value of 1 Ohm, i.e. transforming it to sane default. In case of Intel Merrifield pin control hardware the 20 kOhm sounds plausible because it gives a good trade off between weakness and minimization of leakage current (will be only 50 uA with the above choice). Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
169efc3b |
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03-Jun-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Add I²S bus 2 pins to groups and functions It is useful to control I²S bus 2 pins if we would like to connect an audio codec. Reported-by: mouse <xllacyx@gmail.com> Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
503a02b7 |
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22-Jun-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Update pin names in accordance with official list Some of the pin names were provided officially to the customers in different spelling. We update pin names in accordance with the official list. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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#
fa01aff9 |
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03-Jul-2019 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: Use devm_platform_ioremap_resource() Use the new helper that wraps the calls to platform_get_resource() and devm_ioremap_resource() together. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
f27a0d9a |
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17-Oct-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: merrifield: include bits.h instead of bitops.h The reason of including <linux/bitops.h> here is just for BIT() and Co macros. Since commit 8bd9cb51daac8 ("... Move some macros from <linux/bitops.h> to a new <linux/bits.h> file"), <linux/bits.h> is enough for such compile-time macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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#
e99542fb |
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22-Sep-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: merrifield: Group IO accessors in code Consolidate IO accessors in the code to make maintenance a little bit easier in the future. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5e0b7e7c |
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22-Sep-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: merrifield: Introduce mrfld_read_bufcfg() mrfld_read_bufcfg() helper checks if pin is correct and reads back the current value of corresponding BUFCFG register. While it adds lines of code it will be easier to maintain in the future. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
ac316725 |
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19-Jun-2018 |
Randy Dunlap <rdunlap@infradead.org> |
headers: separate linux/mod_devicetable.h from linux/platform_device.h At over 4000 #includes, <linux/platform_device.h> is the 9th most #included header file in the Linux kernel. It does not need <linux/mod_devicetable.h>, so drop that header and explicitly add <linux/mod_devicetable.h> to source files that need it. 4146 #include <linux/platform_device.h> After this patch, there are 225 files that use <linux/mod_devicetable.h>, for a reduction of around 3900 times that <linux/mod_devicetable.h> does not have to be read & parsed. 225 #include <linux/mod_devicetable.h> This patch was build-tested on 20 different arch-es. It also makes these drivers SubmitChecklist#1 compliant. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kbuild test robot <lkp@intel.com> # drivers/media/platform/vimc/ Reported-by: kbuild test robot <lkp@intel.com> # drivers/pinctrl/pinctrl-u300.c Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
875a92b3 |
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29-Jun-2018 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: Convert to use SPDX identifier Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
dabd4bc6 |
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10-Nov-2017 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: merrifield: Introduce ACPI device table On Intel Merrifield the pin control device is a separate IP block without any PCI ID assigned. Though, recently we got an allocated ACPI ID for it, so, let's use fresh ID. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
5d996132 |
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04-Aug-2017 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: merrifield: Correct UART pin lists UART pin lists consist GPIO numbers which is simply wrong. Replace it by pin numbers. Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
19b26d92 |
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24-Jan-2017 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: merrifield: Add missed check in mrfld_config_set() Not every pin can be configured. Add missed check to prevent access violation. Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
b9aa65ba |
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27-Oct-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: merrifield: Add pin config group handlers Pin config get() and set() handlers for pin groups were previously not implemented by this driver. The pin_config_group_set() is particularly useful for applying a common config setting to all pins in a specified group with a single call, without the caller needing to reference each individual pin by name. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
c11a0442 |
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31-Aug-2016 |
Vincent Stehlé <vincent.stehle@intel.com> |
pinctrl: intel: merrifield: fix dup size in probe In function mrfld_pinctrl_probe(), when duplicating the mrfld_families array the requested memory region length is multiplied once too many by the number of elements in the original array. Fix this to spare some memory. Fixes: 4e80c8f505741cbd ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Vincent Stehlé <vincent.stehle@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
e95d0dfb |
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02-Aug-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: merrifield: Add missed header On x86 builds the absense of <linux/io.h> makes static analyzer and compiler unhappy which fails to build the driver. CHECK drivers/pinctrl/intel/pinctrl-merrifield.c drivers/pinctrl/intel/pinctrl-merrifield.c:518:17: error: undefined identifier 'readl' drivers/pinctrl/intel/pinctrl-merrifield.c:570:17: error: undefined identifier 'readl' drivers/pinctrl/intel/pinctrl-merrifield.c:575:9: error: undefined identifier 'writel' drivers/pinctrl/intel/pinctrl-merrifield.c:645:17: error: undefined identifier 'readl' CC drivers/pinctrl/intel/pinctrl-merrifield.o drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_pin_dbg_show’: drivers/pinctrl/intel/pinctrl-merrifield.c:518:10: error: implicit declaration of function ‘readl’ [-Werror=implicit-function-declaration] value = readl(bufcfg); ^ drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_update_bufcfg’: drivers/pinctrl/intel/pinctrl-merrifield.c:575:2: error: implicit declaration of function ‘writel’ [-Werror=implicit-function-declaration] writel(value, bufcfg); ^ cc1: some warnings being treated as errors Add header to the top of the module. Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4e80c8f5 |
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23-Jun-2016 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: Add Intel Merrifield pin controller support This driver adds pinctrl support for Intel Merrifield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver (gpio-intel-mid.c) will be updated accordingly to support pinctrl interface. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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