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5ce3422e |
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30-Oct-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: jasperlake: Switch to use Intel pin control PM ops The main driver conditionally exports the PM ops structure. Switch this driver to use it instead of customly wrapped one. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231030120734.2831419-12-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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34393c36 |
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15-Aug-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: Switch to use exported namespace We already have a few symbols exported in the namespace. Let's do the same for others (except PM for now). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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6ab57fb3 |
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19-Dec-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: jasperlake: Replace JSL_COMMUNITY() by INTEL_COMMUNITY_GPPS() Use INTEL_COMMUNITY_GPPS() common macro instead custom JSL_COMMUNITY(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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cdd8fc2d |
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11-Nov-2020 |
Evan Green <evgreen@chromium.org> |
pinctrl: jasperlake: Fix HOSTSW_OWN offset GPIOs that attempt to use interrupts get thwarted with a message like: "pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's owned by ACPI. Fixes: e278dcb7048b1 ("pinctrl: intel: Add Intel Jasper Lake pin controller support") Cc: stable@vger.kernel.org Signed-off-by: Evan Green <evgreen@chromium.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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59024c93 |
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10-Nov-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: jasperlake: Unhide SPI group of pins If the group of pins is hidden in the pin list it affects the register offset calculation despite fixed GPIO base. Hence, the offsets of all pins after the hidden group are broken. Instead we have to unhide the group and use a flag to exclude it from GPIO number space. Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support") Reported-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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5aa5541e |
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11-Nov-2020 |
Evan Green <evgreen@chromium.org> |
pinctrl: jasperlake: Fix HOSTSW_OWN offset GPIOs that attempt to use interrupts get thwarted with a message like: "pin 161 cannot be used as IRQ" (for instance with SD_CD). This is because the HOSTSW_OWN offset is incorrect, so every GPIO looks like it's owned by ACPI. Fixes: e278dcb7048b1 ("pinctrl: intel: Add Intel Jasper Lake pin controller support") Cc: stable@vger.kernel.org Signed-off-by: Evan Green <evgreen@chromium.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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bf8b7e68 |
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10-Nov-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: jasperlake: Unhide SPI group of pins If the group of pins is hidden in the pin list it affects the register offset calculation despite fixed GPIO base. Hence, the offsets of all pins after the hidden group are broken. Instead we have to unhide the group and use a flag to exclude it from GPIO number space. Fixes: e278dcb7048b ("pinctrl: intel: Add Intel Jasper Lake pin controller support") Reported-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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e278dcb7 |
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13-Apr-2020 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: intel: Add Intel Jasper Lake pin controller support This driver adds pinctrl/GPIO support for Intel Jasper Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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