ath9k: ar9003_2p2_initvals: Remove unused const variables

Fixes the following W=1 kernel build warning(s):

drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h:1734:18: warning: ‘ar9300PciePhy_clkreq_disable_L1_2p2’ defined but not used [-Wunused-const-variable=]
drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h:1727:18: warning: ‘ar9300PciePhy_clkreq_enable_L1_2p2’ defined but not used [-Wunused-const-variable=]

Cc: QCA ath9k Development <ath9k-devel@qca.qualcomm.com>
Cc: Kalle Valo <kvalo@codeaurora.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: linux-wireless@vger.kernel.org
Cc: netdev@vger.kernel.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20201102112410.1049272-14-lee.jones@linaro.org

ath9k: Update AR9003 2.2 initvals

HW peak detect calibration would fail for AR9300 chips and
we went for implementing the SW way of doing it instead of
HW doing the peak detect calibration.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>

ath9k_hw: update ar9300 initvals

* rfsat gainchange hysteresis of rf_gain stuck with large
interference present.

Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k: Update high power gain table for AR9300

Now that the Buffalo-specific initvals have been
moved to a separate array, update the default high
power TX gain table for all AR9300 v2.2 devices.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k: Update mac_postamble for AR9003 family

Enable the ALWAYS_KEYSEARCH bit in the initvals. Currently
this is done in the driver, but adding this to the initvals
makes it easier to be in sync with the INI files given
by the systems engineering team.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k: Add initval arrays for DFS channels

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k: Fix initvals for freq 2484

This is missing for AR9300, AR9580 and AR9340.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k: Update initvals for AR9300 v2.2

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

Revert "ath9k_hw: Update rx gain initval to improve rx sensitivity"

This reverts commit 68d9e1fa24d9c7c2e527f49df8d18fb8cf0ec943

This change reduces rx sensitivity with no apparent extra benefit.
It looks like it was meant for testing in a specific scenario,
but it was never properly validated.

Cc: rmanohar@qca.qualcomm.com
Cc: stable@vger.kernel.org
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: add tx gain tables for newer devices

Improves stability on affected devices and also fixes the Tx IQ calibration
related regression on some AR9340 devices such as the TP-Link TL-WDR4300.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

Revert "ath9k_hw: Update AR9003 high_power tx gain table"

This reverts commit f74b9d365ddd33a375802b064f96a5d0e99af7c0.

Turns out reverting commit a240dc7b3c7463bd60cf0a9b2a90f52f78aae0fd
"ath9k_hw: Updated AR9003 tx gain table for 5GHz" was not enough to
bring the tx power back to normal levels on devices like the
Buffalo WZR-HP-G450H, this one needs to be reverted as well.

This revert improves tx power by ~10 db on that device

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Cc: stable@vger.kernel.org
Cc: rmanohar@qca.qualcomm.com
Signed-off-by: John W. Linville <linville@tuxdriver.com>

Revert "ath9k_hw: Updated AR9003 tx gain table for 5GHz"

This reverts commit a240dc7b3c7463bd60cf0a9b2a90f52f78aae0fd.

This commit is reducing tx power by at least 10 db on some devices,
e.g. the Buffalo WZR-HP-G450H.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Cc: stable@vger.kernel.org
Cc: rmanohar@qca.qualcomm.com
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k: de-duplicate initvals

The initvals tool from https://github.com/mcgrof/qca-swiss-army-knife has
been modified to detect identical initval tables and replace them with
macros. This patch contains the generated changes.

On MIPS this reduces the binary size by 24 KB with no runtime changes.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Update rx gain initval to improve rx sensitivity

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: remove unused initvals

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Updated AR9003 tx gain table for 5GHz

The 5G Tx gain table w/ XPA is updated to improve spur
performance in high_power Tx gain table.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Update AR9003 initval to improve phase noise

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Updated ar9003 initval table for AR9380

The ar9003 table is updated to increase XLNA BIAS
output driver strengh.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Fix Rx DMA stuck for AR9003 chips

During the endurance testing, rx frames are not getting DMAd from
MAC whereas pcu rx frame counters are getting updated properly.
As per systems team input updated the initval to fix rx dma stuck
issue.

Cc: stable@kernel.org
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Disable Walsh spatial spreading for 2 chains

The Walsh bit is disabled for regulatory consideration.

FCC limit for walsh enable is lower than that for walsh disable. So
disabling walsh bit will not limit tx power/affect tx power even in
cases where we are not FCC limited (most client cards). If the tx
power is not FCC limited, then enabling/disabling walsh bit will
not affect Avg. EVM/overall performance in any visible manner.

Cc: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Update AR9003 high_power tx gain table

The high_power tx gain table is changed to match the low_ob_db tx gain
table for both 5G and 2G.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Update the radio parameters related to high_power

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Remove read-only registers from AR9003 intervals

This patch removes read only registers that cause invalid
address access and also updates index for measurement filter
calibration window size.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Disable power detector calibration for AR9003

The power detector calibration is disabled because this block
doesn't exist in AR9003 based chips and also parallel
calibration is enabled otherwise the calibration will never stop.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Update AR9003 interval to improve 5G Tx EVM

The number of temperature reading samples to average
during a Tx packet is decreased to 1 from 2 to improve
5G Tx EVM with chain 0-only mode.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k: Drag the driver to the year 2011

The Times They Are a-Changin'.

Signed-off-by: Sujith Manoharan <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: update AR9003 low_ob_db_tx_gain to improve spur performance

Signed-off-by: Rajkumar Manoharan <rmanoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: update Ar9003 intervals to fix carrier leak

Signed-off-by: Rajkumar Manoharan <rmanoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: ASPM interoperability fix for AR9380/AR9382

There is an interoperability with AR9382/AR9380 in L1 state with a
few root complexes which can cause a hang. This is fixed by
setting some work around bits on the PCIE PHY. We fix by using
a new ini array to modify these bits when the radio is idle.

Cc: stable@kernel.org
Cc: Jack Lee <jack.lee@atheros.com>
Cc: Carl Huang <carl.huang@atheros.com>
Cc: David Quan <david.quan@atheros.com>
Cc: Nael Atallah <nael.atallah@atheros.com>
Cc: Sarvesh Shrivastava <sarvesh.shrivastava@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: update AR9003 initvals to improve carrier leak calibration/correction

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: update AR9003 initvals for improved radar detection

Reduces the likelihood of false pulse detects in the hardware

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: Fix TX carrier leakage for IEEE compliance on AR9003 2.2

This updates the initvals for the AR9003 2.2 chipsets. The initvals
are the initial register values we use for our registers upon hardware
reset. This synchs up the initvals to match what our latest recommendation
from our systems engineering team.

The description of changes in this update:

Improves ability to support very strong Rx conditions.
Enhances DFS support for AP-mode.
Improves performance of Tx carrier leak calibration.
Adds support for Japan channel 14 Tx filtering requirements.
Improves Tx power accuracy.

Impact:

Update required to address degraded throughput at very short range.
Update required for AP-mode DFS certification.
Update required to comply to IEEE Tx carrier leak specification.
May not meet expected +/- 2 dB Tx power accuracy without update.

The most important fix here would be the TX carrier leakage required
to comply with IEEE 802.11 specifications. The group of changes have
been tested all together in one release.

References:

Osprey 2.2 header file ver #33

Checksums:

$ ./initvals -f ar9003-2p2
0x000000004a488fc7 ar9300_2p2_radio_postamble
0x0000000046cb1300 ar9300Modes_lowest_ob_db_tx_gain_table_2p2
0x00000000e912711f ar9300Modes_fast_clock_2p2
0x0000000037ac0ee8 ar9300_2p2_radio_core
0x00000000047a7700 ar9300Common_rx_gain_table_merlin_2p2
0x0000000003f783bb ar9300_2p2_mac_postamble
0x00000000301fc841 ar9300_2p2_soc_postamble
0x000000005ec8075f ar9200_merlin_2p2_radio_core
0x0000000083372ffa ar9300_2p2_baseband_postamble
0x00000000c4f59974 ar9300_2p2_baseband_core
0x00000000e20d2e72 ar9300Modes_high_power_tx_gain_table_2p2
0x000000007fd55c70 ar9300Modes_high_ob_db_tx_gain_table_2p2
0x0000000029495000 ar9300Common_rx_gain_table_2p2
0x0000000042cb1300 ar9300Modes_low_ob_db_tx_gain_table_2p2
0x00000000c4739cd6 ar9300_2p2_mac_core
0x000000003521a300 ar9300Common_wo_xlna_rx_gain_table_2p2
0x00000000a15ccf1b ar9300_2p2_soc_preamble
0x0000000029734396 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
0x000000002d834396 ar9300PciePhy_clkreq_enable_L1_2p2
0x0000000029834396 ar9300PciePhy_clkreq_disable_L1_2p2

$ ./initvals -f ar9003-2p2 | sha1sum
0ceddb5cf66737610fb51f04cf3e9ff71870c7b4 -

Cc: stable@kernel.org
Cc: Yixiang Li <yixiang.li@atheros.com>
Cc: Don Breslin <don.breslin@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: update 5 GHz tx gain tables for femless and high power PA

This updates the initvals for AR9003 to adjust the 5 GHz tx gain
tables for femless and high power PA.

References:

Osprey 2.0 header file ver 72
Osprey 2.2 header file ver 20

Checksums:

$ ./initvals -f ar9003-2p0
0x00000000c2bfa7d5 ar9300_2p0_radio_postamble
0x00000000ada2b114 ar9300Modes_lowest_ob_db_tx_gain_table_2p0
0x00000000e0bc2c84 ar9300Modes_fast_clock_2p0
0x00000000056eaf74 ar9300_2p0_radio_core
0x0000000000000000 ar9300Common_rx_gain_table_merlin_2p0
0x0000000078658fb5 ar9300_2p0_mac_postamble
0x0000000023235333 ar9300_2p0_soc_postamble
0x0000000054d41904 ar9200_merlin_2p0_radio_core
0x00000000748572cf ar9300_2p0_baseband_postamble
0x000000009aa5a0a4 ar9300_2p0_baseband_core
0x000000003dffa526 ar9300Modes_high_power_tx_gain_table_2p0
0x000000001cfda724 ar9300Modes_high_ob_db_tx_gain_table_2p0
0x0000000011302700 ar9300Common_rx_gain_table_2p0
0x00000000e3eab114 ar9300Modes_low_ob_db_tx_gain_table_2p0
0x00000000c9d66d40 ar9300_2p0_mac_core
0x000000001e1d0800 ar9300Common_wo_xlna_rx_gain_table_2p0
0x00000000a0c54980 ar9300_2p0_soc_preamble
0x00000000292e2544 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0
0x000000002d3e2544 ar9300PciePhy_clkreq_enable_L1_2p0
0x00000000293e2544 ar9300PciePhy_clkreq_disable_L1_2p0

$ ./initvals -f ar9003-2p2
0x00000000c2bfa7d5 ar9300_2p2_radio_postamble
0x00000000ada2b114 ar9300Modes_lowest_ob_db_tx_gain_table_2p2
0x00000000e0bc2c84 ar9300Modes_fast_clock_2p2
0x00000000056eaf74 ar9300_2p2_radio_core
0x0000000000000000 ar9300Common_rx_gain_table_merlin_2p2
0x0000000078658fb5 ar9300_2p2_mac_postamble
0x0000000023235333 ar9300_2p2_soc_postamble
0x0000000054d41904 ar9200_merlin_2p2_radio_core
0x000000008475a084 ar9300_2p2_baseband_postamble
0x000000009aaafd90 ar9300_2p2_baseband_core
0x000000003dffa526 ar9300Modes_high_power_tx_gain_table_2p2
0x000000001cfda724 ar9300Modes_high_ob_db_tx_gain_table_2p2
0x0000000011302700 ar9300Common_rx_gain_table_2p2
0x00000000a9a2b114 ar9300Modes_low_ob_db_tx_gain_table_2p2
0x00000000a9d66d40 ar9300_2p2_mac_core
0x000000001e1d0800 ar9300Common_wo_xlna_rx_gain_table_2p2
0x00000000a0c531c8 ar9300_2p2_soc_preamble
0x00000000292e2544 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
0x000000002d3e2544 ar9300PciePhy_clkreq_enable_L1_2p2
0x00000000293e2544 ar9300PciePhy_clkreq_disable_L1_2p2

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

ath9k_hw: add support for the AR9003 2.2

The checksums of the initvals are:

initvals -f ar9003-2p2
0x00000000c2bfa7d5 ar9300_2p2_radio_postamble
0x00000000ada2b114 ar9300Modes_lowest_ob_db_tx_gain_table_2p2
0x00000000e0bc2c84 ar9300Modes_fast_clock_2p2
0x00000000056eaf74 ar9300_2p2_radio_core
0x0000000000000000 ar9300Common_rx_gain_table_merlin_2p2
0x0000000078658fb5 ar9300_2p2_mac_postamble
0x0000000023235333 ar9300_2p2_soc_postamble
0x0000000054d41904 ar9200_merlin_2p2_radio_core
0x000000008475a084 ar9300_2p2_baseband_postamble
0x000000009aaafd90 ar9300_2p2_baseband_core
0x000000003df9a326 ar9300Modes_high_power_tx_gain_table_2p2
0x000000001cfba124 ar9300Modes_high_ob_db_tx_gain_table_2p2
0x0000000011302700 ar9300Common_rx_gain_table_2p2
0x00000000a9a2b114 ar9300Modes_low_ob_db_tx_gain_table_2p2
0x00000000a9d66d40 ar9300_2p2_mac_core
0x000000001e1d0800 ar9300Common_wo_xlna_rx_gain_table_2p2
0x00000000a0c531c8 ar9300_2p2_soc_preamble
0x00000000292e2544 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
0x000000002d3e2544 ar9300PciePhy_clkreq_enable_L1_2p2
0x00000000293e2544 ar9300PciePhy_clkreq_disable_L1_2p2

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>