History log of /linux-master/drivers/gpu/drm/i915/intel_clock_gating.c
Revision Date Author Comments
# 4973e632 26-Apr-2024 Jani Nikula <jani.nikula@intel.com>

drm/i915/display: split out intel_fbc_regs.h from i915_reg.h

Clean up i915_reg.h.

v2: Drop chicken regs and comments (Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/aa9b5d8adefbe97e1e37c9cfada3ab1581b0e8d5.1714128645.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>


# 326e30e4 20-Mar-2024 Lucas De Marchi <lucas.demarchi@intel.com>

drm/i915: Drop dead code for pvc

PCI IDs for PVC were never added and platform always marked with
force_probe. Drop what's not used and rename some places as needed.

The registers not used anymore are also removed.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Tvrtko Ursulin <tursulin@ursulin.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320060543.4034215-6-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>


# cb4046d2 20-Mar-2024 Lucas De Marchi <lucas.demarchi@intel.com>

drm/i915: Drop dead code for xehpsdv

PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.

The registers not used anymore are also removed.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Tvrtko Ursulin <tursulin@ursulin.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320060543.4034215-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>


# f26b6af5 23-Jan-2024 Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915/fbc: Move DPFC_CHICKEN programming into intel_fbc_program_workarounds()

Move all DPFC_CHICKEN programming into intel_fbc_program_workarounds().
We already have one thing programmed there, whereas the rest is strewn
about in intel_display_wa_apply() and init_clock_gating(). Since we have
a single place doing all the programming (and it's serialized by the
crtc commits) there should be no danger of rmw races.

Other FBC related workarounds also exist, but those require fiddling
with other registers that may also get programmed from other places,
so we'll need to think harder what to do with those.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240123090051.29818-2-ville.syrjala@linux.intel.com
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>


# da1bc5cc 06-Sep-2023 Matt Roper <matthew.d.roper@intel.com>

drm/i915/display: Apply workarounds during display init

Rather than applying display workarounds as part of
intel_clock_gating_init() (which in turn is confusingly called from
i915_gem_init during device probe), handle them at the point we're
actually initializing the display hardware. This will also ensure that
these workarounds are properly applied during display initialization on
the Xe driver, which re-uses i915's display code, but does not call
i915's gem init.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230906234732.3728630-10-matthew.d.roper@intel.com


# 53dd7b1f 06-Sep-2023 Matt Roper <matthew.d.roper@intel.com>

drm/i915/display: Extract display workarounds from clock gating init

Several of the register updates that are currently done in the clock
gating init functions are actually display workarounds that should move
into the display-specific part of the code. Furthermore, some of the
registers being programmed don't even have anything to do with clock
gating at all.

Extract the display workarounds for gen11 and later platforms to a
dedicated display/intel_display_wa.c file to keep these separate from
the SOC / sgunit clock gating that we need on some platforms. The gen11
cutoff here is selected somewhat arbitrarily; this is the point where
workarounds were first assigned dedicated lineage numbers that can be
easily looked up and confirmed in the modern workaround database. It
also avoids any confusion on older platforms where the exact boundaries
between display/GT/other IP blocks wasn't as well-defined as it is
today.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230907001009.3732474-2-matthew.d.roper@intel.com


# 3d0a1688 06-Sep-2023 Matt Roper <matthew.d.roper@intel.com>

drm/i915/adlp: Stop calling gen12lp_init_clock_gating()

The only programming that happens in gen12lp_init_clock_gating is for
display workarounds that are specific to display version 12 and are not
relevant to ADL-P's display version 13.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230906234732.3728630-8-matthew.d.roper@intel.com


# 7ed888fa 06-Sep-2023 Matt Roper <matthew.d.roper@intel.com>

drm/i915: Stop forcing clock gating init for future platforms

In the early days of i915, pretty much every platform needed to
initialize _something_ in the clock gating init functions. In some
cases the items initialized were inside the GT (and really should have
been initialized through the GT workaround infrastructure instead).
In other cases they were display programming (sometimes not even related
to "clock gating" at all!) which probably needs to move inside the
display-specific code. The number of initialization tasks that are
truly "clock gating" and don't fall within the GT or display domains is
relatively limited. Let's stop forcing future platforms to always
define a clock gating init hook.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230906234732.3728630-7-matthew.d.roper@intel.com


# eaeb4b36 16-Aug-2023 Matt Roper <matthew.d.roper@intel.com>

drm/i915/dg2: Drop pre-production GT workarounds

DG2 first production steppings were C0 (for DG2-G10), B1 (for DG2-G11),
and A1 (for DG2-G12). Several workarounds that apply onto to
pre-production hardware can be dropped. Furthermore, several
workarounds that apply to all production steppings can have their
conditions simplified to no longer check the GT stepping.

v2:
- Keep Wa_16011777198 in place for now; it will be removed separately
in a follow-up patch to keep review easier.

Bspec: 44477
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230816214201.534095-10-matthew.d.roper@intel.com


# b1c52560 01-Aug-2023 Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

drm/i915/kbl: s/KBL/KABYLAKE for platform/subplatform defines

Follow consistent naming convention. Replace KBL with
KABYLAKE.Replace IS_KBL_GRAPHICS_STEP with
IS_KABYLAKE () && IS_GRAPHICS_STEP().

v2:
- s/KBL/kbl in the subject prefix(Anusha)

v3:
- Unrolled wrapper IS_KBL_GRAPHICS_STEP.
- Replace with IS_PLATFORM && DISPLAY_STEP(tvrtko/jani)

v4:
- Removed unused macro.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Anusha Srivatsa <Anusha.Srivatsa@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230801135344.3797924-5-dnyaneshwar.bhadane@intel.com


# 8a824f8f 09-Jun-2023 Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hsw

Bspec asks us to unmask "vblank to registers" in the DPRS unit.

Note that I was unable to observe any change in hardware
behviour due to this bit on HSW. But let's do this anyway
in case it matters in some cases, and the corresponding bit
on BDW is abolutely critical as without it the hardware
won't generate any vblanks whatsoever after PSR exit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-10-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>


# a77c3fe3 09-Jun-2023 Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw

Implement WaPsrDPAMaskVBlankInSRD:hsw, which makes the hardware
generate the extra vblank between link training and first frame
being transmitted. This is the same thing that's controlled by
TRANS_CHICKEN[21] on skl+ (but due to the funky double buffering
it's effectively always at the rest value after DC5 exit). So
for consistent behaviour we want every platform to generate said
vblank. BDW is already setting this up correctly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-9-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>


# 2590ef92 11-Apr-2023 Ville Syrjälä <ville.syrjala@linux.intel.com>

drm/i915/psr: Define more PSR mask bits

Define more of the PSR mask bits, and describe in detail
what some of them do. Even if we don't set them all from
the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun, and re-reverse engineering the behaviour every
time is time consuming (even if a bit more fun than spec
trawling).

v2: Moar bits
Put the description into a comment to be easily available
v2: Fix the BDW_UNMASK_VBL_TO_REGS_IN_SRD/HSW_UNMASK_VBL_TO_REGS_IN_SRD
description
Rebase due to intel_psr_regs.h

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230411191429.29895-6-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>


# 476f62b8 18-Apr-2023 Jani Nikula <jani.nikula@intel.com>

drm/i915: use explicit includes for i915_reg.h and i915_irq.h

A lot of places include i915_reg.h implicitly via i915_irq.h, which gets
included implicitly via intel_display_trace.h. Remove the includes from
the headers, and include i915_reg.h and i915_irq.h explicitly where
needed.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230419094243.366821-1-jani.nikula@intel.com


# 1d1e434db 03-Apr-2023 Jani Nikula <jani.nikula@intel.com>

drm/i915/clock: mass rename dev_priv to i915

Follow the contemporary naming style. Include some indentation fixes
while at it on the affected statements.

One function needs to keep using dev_priv due to implicit dev_priv usage
in a macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230403122428.3526263-2-jani.nikula@intel.com


# d670c78e 03-Apr-2023 Jani Nikula <jani.nikula@intel.com>

drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch]

Observe that intel_pm.[ch] is now purely about clock gating, so rename
them to intel_clock_gating.[ch]. Rename the functions to
intel_clock_gating_*() to follow coding conventions.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230403122428.3526263-1-jani.nikula@intel.com