#
8de7948d |
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02-Apr-2024 |
Asad Kamal <asad.kamal@amd.com> |
drm/amd/pm: Update uclk/sclk limit report format Use OD (pp_od_clk_voltage) interface to report current limits, default or those set by user, for SCLK and UCLK on aldebaran. Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b2207dc6 |
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27-Mar-2024 |
Ma Jun <Jun.Ma2@amd.com> |
drm/amdgpu/pm: Add support for MACO flag checking Add support for MACO flag checking. MACO mode only works if BACO is supported. Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1b199594 |
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24-Mar-2024 |
Ma Jun <Jun.Ma2@amd.com> |
drm/amdgpu/pm: Change the member function name in pp_hwmgr_func and pptable_funcs Use a unified and more explicit name get_bamaco_support to replace is_baco_support and get_asic_baco_capability Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b485b899 |
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27-Feb-2024 |
Asad Kamal <asad.kamal@amd.com> |
drm/amd/pm: Fix esm reg mask use to get pcie speed Fix mask used for esm ctrl register to get pcie link speed on smu_v11_0_3, smu_v13_0_2 & smu_v13_0_6 Fixes: 511a95552ec8 ("drm/amd/pm: Add SMU 13.0.6 support") Fixes: c05d1c401572 ("drm/amd/swsmu: add aldebaran smu13 ip support (v3)") Fixes: f1c378593153 ("drm/amd/powerplay: add Arcturus support for gpu metrics export") Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a3c45818 |
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27-Feb-2024 |
Asad Kamal <asad.kamal@amd.com> |
drm/amd/pm: Skip reporting pcie width/speed on vfs Skip reporting pcie link width/speed on vfs for smu_v13_0_6 & smu_v13_0_2 Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f21682b3 |
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12-Nov-2023 |
Heiner Kallweit <hkallweit1@gmail.com> |
drm/amd/pm: Remove I2C_CLASS_SPD support I2C_CLASS_SPD was used to expose the EEPROM content to user space, via the legacy eeprom driver. Now that this driver has been removed, we can remove I2C_CLASS_SPD support. at24 driver with explicit instantiation should be used instead. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
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#
b0e5c88d |
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23-Nov-2023 |
Dinghao Liu <dinghao.liu@zju.edu.cn> |
drm/amd/pm: fix a memleak in aldebaran_tables_init When kzalloc() for smu_table->ecc_table fails, we should free the previously allocated resources to prevent memleak. Fixes: edd794208555 ("drm/amd/pm: add message smu to get ecc_table v2") Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7a88f23e |
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23-Nov-2023 |
Dinghao Liu <dinghao.liu@zju.edu.cn> |
drm/amd/pm: fix a memleak in aldebaran_tables_init When kzalloc() for smu_table->ecc_table fails, we should free the previously allocated resources to prevent memleak. Fixes: edd794208555 ("drm/amd/pm: add message smu to get ecc_table v2") Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5bd8e05f |
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24-Oct-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amd/pm: call smu_cmn_get_smc_version in is_mode1_reset_supported. is_mode1_reset_supported may be called before smu init, when smu_context is unitialized in driver load/unload test. Call smu_cmn_get_smc_version explicitly in is_mode1_reset_supported. v2: apply to aldebaran in case is_mode1_reset_supported will be uncommented (Candice Li) Fixes: 710d9caec70c ("drm/amd/pm: drop most smu_cmn_get_smc_version in smu") Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Candice Li <candice.li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
19589468 |
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11-Oct-2023 |
Ma Jun <Jun.Ma2@amd.com> |
drm/amd/pm: Support for getting power1_cap_min value Support for getting power1_cap_min value on smu13 and smu11. For other Asics, we still use 0 as the default value. Signed-off-by: Ma Jun <Jun.Ma2@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
710d9cae |
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10-Oct-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amd/pm: drop most smu_cmn_get_smc_version in smu smu_check_fw_version is called in smu hw init, thus smu if version and version are garenteed to be stored in smu context. No need to call smu_cmn_get_smc_version again after system boot up. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8a2b5139 |
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04-Oct-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Refactor FRU product information Keep FRU related information together in a separate structure. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c01c8523 |
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20-Sep-2023 |
Le Ma <le.ma@amd.com> |
drm/amd/pm: integrate plpd allow/disallow into select_xgmi_plpd_policy in ppt level The allow_xgmi_power_down(true/false) will be generally replaced by: - allow: select_xgmi_plpd_policy(XGMI_PLPD_DEFAULT) - disallow: select_xgmi_plpd_policy(XGMI_PLPD_DISALLOW) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
14bf1c47 |
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03-Apr-2023 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Optimize emit_clock_levels for aldebaran - part 3 split switch statement into two and consolidate the common code for printing most of the types of clock speeds Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d62846f7 |
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03-Apr-2023 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Optimize emit_clock_levels for aldebaran - part 2 Use variables to remove ternary expression in print statement and improve readability. This will help to optimize the code duplication in the switch statement Also Changed: replaced single_dpm_table->count as iterator in for loops with safer clocks_num_levels value replaced dpm_table.value usage with local var clocks_mhz Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2ecf214b |
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03-Apr-2023 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Optimize emit_clock_levels for aldebaran - part 1 Use variables to remove the multiple nested ternary expressions and improve readability. This will help to optimize the code duplication in the switch statement Also Changed: Modify function aldebaran_get_clk_table to void function as it always returns 0 Use const string "attempt_string" to cut down on repetition Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bc22d9e0 |
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08-Apr-2022 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Replace print_clock_levels with emit_clock_levels for aldebaran Replace print_clock_levels with emit_clock_levels for aldebaran * replace .print_clk_levels with .emit_clk_levels in aldebaran_ppt_funcs * added extra parameter int *offset * removed var size, uses arg *offset instead * removed call to smu_cmn_get_sysfs_buf * errors are returned to caller * returns 0 on success additional incidental changes * changed type of vars i, now to remove comparing mismatch types * renamed var s/now/cur_value/ * switch statement default now returns -EINVAL * RAS Recovery returns -EBUSY Based on commit b06b48d7ddae ("amdgpu/pm: Implement emit_clk_levels for navi10") Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ddf1639b |
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23-Aug-2023 |
Colin Ian King <colin.i.king@gmail.com> |
drm/amd: Fix spelling mistake "throtting" -> "throttling" There is a spelling mistake in variable throtting_events, rename it to throttling_events. Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9366c2e8 |
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10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWER Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4c64f2e4 |
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10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Fix the return for average power on aldebaran Aldebaran can only return average socket power for the first die. The other dies return 0. Instead of returning a bad value, return -EOPNOTSUPP so that the attribute will be hidden. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
05228211 |
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10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Drop unnecessary helper for aldebaran aldebaran_get_gpu_power() is only called by one place and just calls aldebaran_get_smu_metrics_data(), so drop the helper. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47f1724d |
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10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER` Some GPUs have been overloading average power values and input power values. To disambiguate these, introduce a new `AMDGPU_PP_SENSOR_GPU_INPUT_POWER` and the GPUs that share input power update to use this instead of average power. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2746 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8c3d5b40 |
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31-Jul-2023 |
Ran Sun <sunran001@208suo.com> |
drm/amd/pm: Clean up errors in aldebaran_ppt.c Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line ERROR: space required after that ',' (ctx:VxV) ERROR: spaces required around that '=' (ctx:VxW) ERROR: else should follow close brace '}' Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
62b73bd5 |
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20-Jun-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amd/pm: fix smu i2c data read risk the smu driver_table is used for all types of smu tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..). it is necessary to hold this lock to avoiding data tampering during the i2c read operation. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d934e537 |
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20-Jun-2023 |
Yang Wang <kevinyang.wang@amd.com> |
drm/amd/pm: fix smu i2c data read risk the smu driver_table is used for all types of smu tables data transcation (e.g: PPtable, Metrics, i2c, Ecc..). it is necessary to hold this lock to avoiding data tampering during the i2c read operation. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
9661bf68 |
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21-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Keep interface version in PMFW header Use the interface version directly from PMFW interface header file rather than keeping another definition in common smu13 file. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b31d6ada |
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28-Sep-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: disable cstate feature for gpu reset scenario Suggested by PMFW team and same as what did for gfxoff feature. This can address some Mode1Reset failures observed on SMU13.0.0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0.x
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#
3059cd8c |
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28-Sep-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: disable cstate feature for gpu reset scenario Suggested by PMFW team and same as what did for gfxoff feature. This can address some Mode1Reset failures observed on SMU13.0.0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.0.x Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ceb18036 |
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10-May-2022 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Fix possible array out-of-bounds if SCLK levels != 2 [v2] simplified fix after Lijo's feedback removed clocks.num_levels from calculation of loop count removed unsafe accesses to shim table freq_values retained corner case output only min,now if clocks.num_levels == 1 && now > min [v1] added a check to populate and use SCLK shim table freq_values only if using dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL or AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM removed clocks.num_levels from calculation of shim table size removed unsafe accesses to shim table freq_values output gfx_table values if using other dpm levels added check for freq_match when using freq_values for when now == min_clk == Test == LOGFILE=aldebaran-sclk.test.log AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES="pp_od_clk_voltage pp_dpm_sclk" for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
543faf57 |
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29-Apr-2022 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Fix incorrect variable for size of clocks array [v2] No Changes, added RB [v1] Size of pp_clock_levels_with_latency is PP_MAX_CLOCK_LEVELS, not MAX_NUM_CLOCKS. Both are currently defined as 16, modifying in case one value is modified in future Changed code in both arcturus and aldabaran. Also removed unneeded var count, and used min_t function Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
da1db031 |
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26-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context So we can eventaully use them in the common smu code for accessing the SMU mailboxes without needing a lot of per asic logic in the common code. Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cbd3e844 |
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20-May-2022 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amdgpu: print umc correctable error address Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2f6247da |
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20-May-2022 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amdgpu/pm: support mca_ceumc_addr in ecctable SMU add a new variable mca_ceumc_addr to record umc correctable error address in EccInfo table, driver side add EccInfo_V2_t to support this feature Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b0f4d663 |
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18-May-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Fix missing thermal throttler status On aldebaran, when thermal throttling happens due to excessive GPU temperature, the reason for throttling event is missed in warning message. This patch fixes it. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a93d938 |
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29-Mar-2022 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Use metrics data function to get unique_id for Aldebaran This is abstracted well enough in the get_metrics_data function, so use the function Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d510eccf |
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03-Mar-2022 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amd/pm: add send bad channel info function support message SMU update bad channel info to update HBM bad channel info in OOB table Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d282665 |
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07-Dec-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: update the data type for retrieving enabled ppfeatures Use uint64_t instead of an array of uint32_t. This can avoid some non-necessary intermediate uint32_t -> uint64_t conversions. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
00d6936d |
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04-Feb-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Set FRU bus for Aldebaran and Vega 20 The FRU and RAS EEPROMs share the same I2C bus on Aldebaran and Vega 20 ASICs. Set the FRU bus "pointer" to this single bus, as access to the FRU is sought through that bus "pointer" and not through the RAS bus "pointer". Cc: Roy Sun <Roy.Sun@amd.com> Cc: Alex Deucher <Alexander.Deucher@amd.com> Fixes: 2f60dd50769efc ("drm/amd: Expose the FRU SMU I2C bus") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e281d594 |
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26-Jan-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/swsmu/i2c: return an error if the SMU is not running Return an error if someone tries to use the i2c bus when the SMU is not running. Otherwise we can end up sending commands to the SMU which will either get ignored or could cause other issues depending on what state the GPU and SMU are in. Cc: Luben.Tuikov@amd.com Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2f60dd50 |
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19-Jan-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amd: Expose the FRU SMU I2C bus Expose both SMU I2C buses. Some boards use the same bus for both the RAS and FRU EEPROMs and others use different buses. This enables the additional I2C bus and sets the right buses to use for RAS and FRU EEPROM access. Cc: Roy Sun <Roy.Sun@amd.com> Co-developed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
56383e8f |
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28-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop unneeded smu->sensor_lock As all those related APIs are already well protected by adev->pm.mutex and smu->message_lock. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
da11407f |
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28-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop unneeded smu->metrics_lock As all those related APIs are already well protected by adev->pm.mutex and smu->message_lock. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e0638c7a |
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28-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: drop unneeded lock protection smu->mutex As all those APIs are already protected either by adev->pm.mutex or smu->message_lock. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
837d542a |
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15-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: relocate the power related headers Instead of centralizing all headers in the same folder. Separate them into different folders and place them among those source files those who really need them. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ebfc2533 |
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21-Nov-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: do not expose the smu_context structure used internally in power This can cover the power implementation details. And as what did for powerplay framework, we hook the smu_context to adev->powerplay.pp_handle. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
15084a8e |
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10-Jan-2022 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amd/pm: only send GmiPwrDnControl msg on master die (v3) PMFW only returns 0 on master die and sends NACK back on other dies for the message. v2: only send GmiPwrDnControl msg on master die instead of all dies. v3: remove the pointer check for get_socket_id and get_die_id as they should be present on Aldebaran. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
de0af8a6 |
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13-Dec-2021 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Only overwrite serial if field is empty On Aldebaran, the serial may be obtained from the FRU. Only overwrite the serial with the unique_id if the serial is empty. This will support printing serial numbers for mGPU devices where there are 2 unique_ids for the 2 GPUs, but only one serial number for the board Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4da8b639 |
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17-Dec-2021 |
sashank saye <sashank.saye@amd.com> |
drm/amdgpu: Send Message to SMU on aldebaran passthrough for sbr handling For Aldebaran chip passthrough case we need to intimate SMU about special handling for SBR.On older chips we send LightSBR to SMU, enabling the same for Aldebaran. Slight difference, compared to previous chips, is on Aldebaran, SMU would do a heavy reset on SBR. Hence, the word Heavy instead of Light SBR is used for SMU to differentiate. Reviewed by: Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by: sashank saye <sashank.saye@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3c27abee |
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15-Dec-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Fix xgmi link control on aldebaran Fix the message argument. 0: Allow power down 1: Disallow power down Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
91e16017 |
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14-Dec-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Skip power state allocation Power states are not valid for arcturus and aldebaran, no need to allocate memory. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
edd79420 |
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16-Nov-2021 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amd/pm: add message smu to get ecc_table v2 support ECC TABLE message, this table include umc ras error count and error address v2: add smu version check to query whether support ecctable call smu_cmn_update_table to get ecctable directly Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3ebd8bf0 |
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12-Nov-2021 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: support new mode-1 reset interface (v2) If gpu reset is triggered by ras fatal error, tell it to smu in mode-1 reset message. v2: move mode-1 reset function to aldebaran_ppt.c since it's aldebaran specific currently. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
19e66d51 |
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15-Dec-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Fix xgmi link control on aldebaran Fix the message argument. 0: Allow power down 1: Disallow power down Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d1ac1cb |
|
18-Aug-2021 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: (v2) add limit_type to (pptable_funcs)->set_power_limit signature v2 add check for SMU_DEFAULT_PPT_LIMIT v1 modify (pptable_funcs)->set_power_limit signature modify smu11 set_power_limit signature (arcturus, navi10, sienna_cichlid) modify smu13 set_power_limit signature (aldabaran) modify vangogh_set_power_limit signature (vangogh) === Test === sudo bash AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} LOGFILE=pp_show_power_cap.log cp $LOGFILE{,.old} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES=" power1_cap power2_cap" for f in $FILES do if test -f "$HWMON_DIR/$f"; then echo === $f === >> $LOGFILE cat $HWMON_DIR/$f >> $LOGFILE RESTORE_VALUE=`cat $HWMON_DIR/$f` 2>&1 >> $LOGFILE echo RESTORE_VALUE $RESTORE_VALUE >> $LOGFILE echo 120000000 > $HWMON_DIR/$f sleep 3 cat $HWMON_DIR/$f >> $LOGFILE echo $RESTORE_VALUE > $HWMON_DIR/$f sleep 3 cat $HWMON_DIR/$f >> $LOGFILE else echo === $f === >> $LOGFILE echo File Not Found >> $LOGFILE fi done cat $LOGFILE Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ee121f7e |
|
07-Sep-2021 |
Lang Yu <lang.yu@amd.com> |
drm/amdgpu: fix sysfs_emit/sysfs_emit_at warnings(v2) sysfs_emit and sysfs_emit_at requrie a page boundary aligned buf address. Make them happy! v2: use an inline function. Warning Log: [ 492.545174] invalid sysfs_emit_at: buf:00000000f19bdfde at:0 [ 492.546416] WARNING: CPU: 7 PID: 1304 at fs/sysfs/file.c:765 sysfs_emit_at+0x4a/0xa0 [ 492.654805] Call Trace: [ 492.655353] ? smu_cmn_get_metrics_table+0x40/0x50 [amdgpu] [ 492.656780] vangogh_print_clk_levels+0x369/0x410 [amdgpu] [ 492.658245] vangogh_common_print_clk_levels+0x77/0x80 [amdgpu] [ 492.659733] ? preempt_schedule_common+0x18/0x30 [ 492.660713] smu_print_ppclk_levels+0x65/0x90 [amdgpu] [ 492.662107] amdgpu_get_pp_od_clk_voltage+0x13d/0x190 [amdgpu] [ 492.663620] dev_attr_show+0x1d/0x40 Signed-off-by: Lang Yu <lang.yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8f48ba30 |
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07-Sep-2021 |
Lang Yu <lang.yu@amd.com> |
drm/amdgpu: fix sysfs_emit/sysfs_emit_at warnings(v2) sysfs_emit and sysfs_emit_at requrie a page boundary aligned buf address. Make them happy! v2: use an inline function. Warning Log: [ 492.545174] invalid sysfs_emit_at: buf:00000000f19bdfde at:0 [ 492.546416] WARNING: CPU: 7 PID: 1304 at fs/sysfs/file.c:765 sysfs_emit_at+0x4a/0xa0 [ 492.654805] Call Trace: [ 492.655353] ? smu_cmn_get_metrics_table+0x40/0x50 [amdgpu] [ 492.656780] vangogh_print_clk_levels+0x369/0x410 [amdgpu] [ 492.658245] vangogh_common_print_clk_levels+0x77/0x80 [amdgpu] [ 492.659733] ? preempt_schedule_common+0x18/0x30 [ 492.660713] smu_print_ppclk_levels+0x65/0x90 [amdgpu] [ 492.662107] amdgpu_get_pp_od_clk_voltage+0x13d/0x190 [amdgpu] [ 492.663620] dev_attr_show+0x1d/0x40 Signed-off-by: Lang Yu <lang.yu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a9bd6db |
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26-Aug-2021 |
Kees Cook <keescook@chromium.org> |
drm/amd/pm: And destination bounds checking to struct copy In preparation for FORTIFY_SOURCE performing compile-time and run-time field bounds checking for memcpy(), memmove(), and memset(), avoid intentionally writing across neighboring fields. The "Board Parameters" members of the structs: struct atom_smc_dpm_info_v4_5 struct atom_smc_dpm_info_v4_6 struct atom_smc_dpm_info_v4_7 struct atom_smc_dpm_info_v4_10 are written to the corresponding members of the corresponding PPTable_t variables, but they lack destination size bounds checking, which means the compiler cannot verify at compile time that this is an intended and safe memcpy(). Since the header files are effectively immutable[1] and a struct_group() cannot be used, nor a common struct referenced by both sides of the memcpy() arguments, add a new helper, amdgpu_memcpy_trailing(), to perform the bounds checking at compile time. Replace the open-coded memcpy()s with amdgpu_memcpy_trailing() which includes enough context for the bounds checking. "objdump -d" shows no object code changes. [1] https://lore.kernel.org/lkml/e56aad3c-a06f-da07-f491-a894a570d78f@amd.com Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Feifei Xu <Feifei.Xu@amd.com> Cc: Likun Gao <Likun.Gao@amd.com> Cc: Jiawei Gu <Jiawei.Gu@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
becf6c95 |
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11-Aug-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/pm: change smu msg's attribute to allow working under sriov the following message is allowed in sriov mode: 1. GetEnabledSmuFeaturesLow 2. GetEnabledSmuFeaturesHigh Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cb5da84a |
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11-Aug-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/pm: change return value in aldebaran_get_power_limit() v1: 1. change return value to avoid smu driver probe fails when FEATURE_PPT is not enabled. 2. if FEATURE_PPT is not enabled, set power limit value to 0. v2: instead dev_err with dev_warn Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
19838cba |
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11-Aug-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/pm: correct DPM_XGMI/VCN_DPM feature name the following feature is wrong, it will cause sysnode of pp_features show error: 1. DPM_XGMI 2. VCN_DPM Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e738c2f0 |
|
09-Jul-2021 |
Darren Powell <darren.powell@amd.com> |
amdgpu/pm: Replace smu12/13 usage of sprintf with sysfs_emit initial modification of files renoir_ppt.c aldebaran_ppt.c yellow_carp_ppt.c === Test === AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} LOGFILE=pp_printf.test.log lspci -nn | grep "VGA\|Display" > $LOGFILE FILES="pp_dpm_sclk pp_power_profile_mode " for f in $FILES do echo === $f === >> $LOGFILE cat $HWMON_DIR/device/$f >> $LOGFILE done cat $LOGFILE Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a3841433 |
|
01-Aug-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/pm: correct aldebaran smu feature mapping FEATURE_DATA_CALCULATIONS correct smu feature mapping: FEATURE_DATA_CALCULATIONS it will cause sysfs node of "pp_features" show error. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
410e302e |
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06-Jul-2021 |
Graham Sider <Graham.Sider@amd.com> |
drm/amdkfd: Update SMI throttle event bitmask Update Arcturus/Aldebaran thermal throttle SMI event path to use ASIC-independent throttler bits when logging. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
54e60654 |
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15-Jul-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Support board calibration on aldebaran Add support for board power calibration on Aldebaran. Board calibration is done after DC offset calibration. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c0838d3a |
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02-Jul-2021 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: The I2C IP doesn't support 0 writes/reads The I2C IP doesn't support writes or reads of 0 bytes. In order for a START/STOP transaction to take place on the bus, the data written/read has to be at least one byte. That is, you cannot generate a write with 0 bytes, just to get the ACK from a device, just so you can probe that device if it is on the bus and so to discover all devices on the bus--you'll have to read at least one byte. Writes of 0 bytes generate no START/STOP on this I2C IP--the bus is not engaged at all. Set the I2C_AQ_NO_ZERO_LEN to the existing I2C quirk tables for Aldebaran, Arcturus, Navi10 and Sienna Cichlid, and add a quirk table to the I2C driver which drives the bus when the SMU doesn't--for instance on Vega20. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Lijo Lazar <Lijo.Lazar@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Lijo Lazar <Lijo.Lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ae87df07 |
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02-Jul-2021 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amd/pm: Add I2C quirk table to Aldebaran Add I2C quirk table to Aldebaran. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Lijo Lazar <Lijo.Lazar@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Lijo Lazar <Lijo.Lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
da98d99b |
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27-Jun-2021 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amd/pm: Simplify managed I2C transfer of Aldebaran Simplify Aldebaran managed I2C transfer function to correctly play with the upper I2C layers. This gets it in line with Navi10, Acturus, and Sienna Cichlid. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Lijo Lazar <Lijo.Lazar@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6588b101 |
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15-Jul-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Support board calibration on aldebaran Add support for board power calibration on Aldebaran. Board calibration is done after DC offset calibration. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
513befa6 |
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11-Jun-2021 |
Stanley.Yang <Stanley.Yang@amd.com> |
drm/amdgpu: message smu to update hbm bad page number Use SMU to update the bad pages rather than directly accessing the EEPROM from the driver. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
076f55a4 |
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09-Jun-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Only primary die supports power data On aldebaran, only primary die fetches valid power data. Show power/energy values as 0 on secondary die. Also, power limit should not be set through secondary die. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
488f211d |
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18-May-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: correct the power limits reporting on OOB supported As OOB(out-of-band) interface may be used to update the power limits. Thus to make sure the power limits reporting of our driver always reflects the correct values, the internal cache must be aligned carefully. V2: add support for out-of-band of other ASICs align cached current power limit with OOB imposed Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-By: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
56d9bf62 |
|
07-Jun-2021 |
Graham Sider <Graham.Sider@amd.com> |
drm/amd/pm: Add aldebaran throttler translation Perform dependent to independent throttle status translation for aldebaran. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ff05bb18 |
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04-Jun-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Remove BACO check for aldebaran BACO/MACO is not applicable for aldebaran. Remove the redundant check. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dd1d82c0 |
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26-May-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/swsmu/aldebaran: fix check in is_dpm_running If smu_cmn_get_enabled_mask() fails, return false to be consistent with other asics. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Lee Jones <lee.jones@linaro.org> Reviewed-by: Lee Jones <lee.jones@linaro.org>
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#
d26ebc58 |
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26-May-2021 |
Lee Jones <lee.jones@linaro.org> |
drm/amd/pm/inc/smu_v13_0: Move table into the only source file that uses it Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../pm/inc/smu_v13_0.h:54:43: warning: ‘smu13_thermal_policy’ defined but not used [-Wunused-const-variable=] Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Kevin Wang <kevin1.wang@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5051cb79 |
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20-May-2021 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amd/pm: fix return value in aldebaran_set_mp1_state() For default cases,we should return 0. Otherwise resume will abort because of the wrong return value. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
78842457 |
|
17-May-2021 |
David M Nieto <david.nieto@amd.com> |
drm/amdgpu/pm: display vcn pp dpm (v4) Enable displaying DPM levels for VCN clocks in swsmu supported ASICs v2: removed set functions for navi, renoir v3: removed set function from arcturus v4: added missing defines in drm_table and remove uneeded goto label in navi10_ppt.c Signed-off-by: David M Nieto <david.nieto@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5709121a |
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13-May-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Reset max GFX clock after disabling determinism When determinism mode is disabled on aldebaran, max GFX clock will be reset to default max frequency value. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e943dd88 |
|
13-May-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Fix showing incorrect frequencies on aldebaran v1: Use the current and custom pstate frequencies to track the current and user-set min/max values in manual and determinism mode. Previously, only actual_* value was used to track the currrent and user requested value. The value will get reassigned whenever user requests a new value with pp_od_clk_voltage node. Hence it will show incorrect values when user requests an invalid value or tries a partial request without committing the values. Separating out to custom and current variable fixes such issues. v2: Remove redundant if-else check Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cfd053be |
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26-Apr-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: expose pmfw attached timestamp on Aldebaran Available with 68.18.0 and later PMFWs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f876549d |
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23-Apr-2021 |
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> |
drm/amd/pm: Update energy_accumulator in gpu metrics Now that it is available. v2: squash in typecast fix (Alex) Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7f353342 |
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09-Apr-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Show updated clocks on aldebaran When GFXCLK range is updated in manual/determinism mode, show the updated min/max clock range. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
96381e3a |
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11-Apr-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Use VBIOS PPTable for aldebaran Keep the logic to force-use VBIOS PPTable in aldebaran rather than in generic SMU13. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
340c571b |
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25-Mar-2021 |
John Clements <john.clements@amd.com> |
drm/amdgpu: add ras aldebaran ras eeprom driver added host to smu cmd to access i2c eeprom Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
928a0fe6 |
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23-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix build warnings Fix header guard and make internal functions static. Fixes the below warnings: drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_reset.h:24:9: warning: '__AMDUGPU_RESET_H__' is used as a header guard here, followed by #define of a different macro [-Wheader-guard] drivers/gpu/drm/amd/amdgpu/aldebaran.c:110:6: warning: no previous prototype for function 'aldebaran_async_reset' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.c:1435:5: warning: no previous prototype for function 'aldebaran_mode2_reset' [-Wmissing-prototypes] Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c941e9fe |
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16-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Add support for reset completion on aldebaran v1: On aldebaran, after hardware context restore, another handshake needs to happen with PMFW so that reset recovery is complete from PMFW side. Treat this as RESET_COMPLETE event for aldebaran. v2: Cleanup coding style, info logs Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e42569d0 |
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16-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Modify mode2 msg sequence on aldebaran v1: During mode2 reset, PCI space is lost after message is sent. Restore PCI space before waiting for response from firmware. v2: Move mode2 sequence to aldebaran and update PMFW version. Handle generic sequence in smu13 without PMFW version check. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1689fca0 |
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16-Mar-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: fix Navi1x runtime resume failure V2 The RLC was put into a wrong state on runtime suspend. Thus the RLC autoload will fail on the succeeding runtime resume. By adding an intermediate PPSMC_MSG_PrepareMp1ForUnload(some GC hard reset involved, designed for PnP), we can bring RLC back into the desired state. V2: integrate INTERRUPTS_ENABLED flag clearing into current mp1 state set routines Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d78b8d6 |
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10-Mar-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amd/pm: correct the gpu metrics version For V1_0 and V1_1, they come with different size. Misuse may cause out of memory access. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6e58941c |
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11-Mar-2021 |
Eric Huang <jinhuieric.huang@amd.com> |
drm/amd/pm: add a new sysfs entry for default power limit Driver doesn't keep the default bootup power limit and expose it to user. As requested we add it in driver. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
775f11aa |
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07-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Enable pp_od_clk_voltage node on aldebaran Use pp_od_clk_voltage node to enable performance determinism and GFX clock min/max range for aldebaran. This is to avoid overload of pp_dpm_sclk and maintain consistency in user lib interfaces. Ex: To enable perf determinism at 900MHz max gfx clock 1) echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level 2) echo s 1 900 > /sys/bus/pci/devices/.../pp_od_clk_voltage 3) echo c > /sys/bus/pci/devices/.../pp_od_clk_voltage Ex: To enable min 500MHz/max 900MHz gfx clocks 1) echo manual > "/sys/bus/pci/devices/.../power_dpm_force_performance_level" 2) echo s 0 500 > "/sys/bus/pci/devices/.../pp_od_clk_voltage" 3) echo s 1 900 > "/sys/bus/pci/devices/.../pp_od_clk_voltage” 4) echo c > "/sys/bus/pci/devices/.../pp_od_clk_voltage” Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bea9cd3f |
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05-Mar-2021 |
Kenneth Feng <kenneth.feng@amd.com> |
drm/amd/pm: add new data in metrics table Export new data in the metrics table for gfx and memory utilization counter, and each hbm temperature as well. v2: change the metrics table version to v1.1 v3: fix the coding style v4: rebase against latest kernel Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25049166 |
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05-Feb-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/pm: add aldebaran serial number support add aldebaran serial number support. (serial number from metrics table) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
65ec7c08 |
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04-Feb-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Enable user min/max gfxclk on aldebaran Aldebaran has fine grained DPM for GFXCLK. Instead of a discrete level, user can specify a min/max range of GFXCLK for any profiling/tuning purpose.This option is available only in manual performance level mode. Select "manual" as power_dpm_force_performance_level and specify the min/max range using pp_dpm_sclk sysfs node. User cannot specify a min/max range outside of the default min/max range of the ASIC. If specified outside the range, values will be bound by the default min/max range. Ex: To use gfxclk min = 600MHz and max = 900MHz echo manual > /sys/bus/pci/devices/.../power_dpm_force_performance_level echo min 600 max 900 > /sys/bus/pci/devices/.../pp_dpm_sclk Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2bb8ac85 |
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04-Feb-2021 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/pm: remove aldebaran serial number support the following message is not supported. PPSMC_MSG_ReadSerialNumTop32 PPSMC_MSG_ReadSerialNumBottom32 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
debd629a |
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29-Jan-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Correct msg status check for powerlimit Status 0 indicates success, fix the check before using PPTable limit Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com>` Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6be64246 |
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05-Mar-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Enable performance determinism on aldebaran Performance Determinism is a new mode in Aldebaran where PMFW tries to maintain sustained performance level. It can be enabled on a per-die basis on aldebaran. To guarantee that it remains within the power cap, a max GFX frequency needs to be specified in this mode. A new power_dpm_force_performance_level, "perf_determinism", is defined to enable this mode in amdgpu. The max frequency (in MHz) can be specified through pp_dpm_sclk. The mode will be disabled once any other performance level is chosen. Ex: To enable perf determinism at 900Mhz max gfx clock echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level echo max 900 > /sys/bus/pci/devices/.../pp_dpm_sclk Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
26256ca8 |
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28-Jan-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Add DCBTC support for aldebaran On aldebaran DCBTC should be run after enabling DPM. DCBTC won't be run if support is not enabled in PPTable. Without PPTable support the message is dummy and will return success always. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d6f19a99 |
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28-Jan-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Fix power limit query on aldebaran Aldebaran doesn't have AC/DC power limits. Separate the implementation from SMU13. Max power limit is queried from PPTable. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ced7e082 |
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12-Jan-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu/pm: Fix reset message mapping on aldebaran Use the correct mapping for mode-reset messages on aldebaran Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
701db675 |
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10-Jan-2021 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu/pm: Remove unsupported MP1 messages from aldebaran PrepareMp1Reset and SoftReset messages are not supported on aldebaran. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b1138d5e |
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28-Nov-2020 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Add atom_smc_dpm_info_v4_10 for aldebaran Add atom_smc_dpm_info_v4_10 that defines board parameters for aldebaran Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com> Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ea9097d9 |
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19-Nov-2020 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu:return true for mode1_reset_support on aldebaran Will remove once validation finished. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5c03e584 |
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19-Nov-2020 |
Feifei Xu <Feifei.Xu@amd.com> |
drm/amdgpu:add smu mode1/2 support for aldebaran Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset. Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions. Add mode2_reset_is_support() for smu->ppt_funcs. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c05d1c40 |
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20-Oct-2020 |
Kevin Wang <kevin1.wang@amd.com> |
drm/amd/swsmu: add aldebaran smu13 ip support (v3) Add initial swSMU support. v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth) v2: switch to thm/mp v13_0 ip headers (Hawking) v3: squash in updates (Alex) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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