#
40356542 |
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16-Apr-2024 |
Sunil Khatri <sunil.khatri@amd.com> |
drm/amdgpu: add protype for print ip state Add the protoype for print ip state to be used to print the registers in devcoredump during a gpu reset. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e21d253b |
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01-Apr-2024 |
Sunil Khatri <sunil.khatri@amd.com> |
drm/amdgpu: add prototype for ip dump Add the prototype to dump ip registers for all ips of different asics and set them to NULL for now. Based on the requirement add a function pointer for each of them. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
037b98a2 |
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08-Nov-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move UVD and VCE sched entity init after sched init We need kernel scheduling entities to deal with handle clean up if apps are not cleaned up properly. With commit 56e449603f0ac5 ("drm/sched: Convert the GPU scheduler to variable number of run-queues") the scheduler entities have to be created after scheduler init, so change the ordering to fix this. v2: Leave logic in UVD and VCE code Fixes: 56e449603f0a ("drm/sched: Convert the GPU scheduler to variable number of run-queues") Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Luben Tuikov <ltuikov89@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: ltuikov89@gmail.com
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#
042a70e4 |
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02-Aug-2023 |
Ran Sun <sunran001@208suo.com> |
drm/amdgpu: Clean up errors in vce_v3_0.c Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25faeddc |
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25-Mar-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: expand cg_flags from u32 to u64 With this, we can support more CG flags. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d82e2c24 |
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15-Sep-2021 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Fix crash on device remove/driver unload Crash: BUG: unable to handle page fault for address: 00000000000010e1 RIP: 0010:vega10_power_gate_vce+0x26/0x50 [amdgpu] Call Trace: pp_set_powergating_by_smu+0x16a/0x2b0 [amdgpu] amdgpu_dpm_set_powergating_by_smu+0x92/0xf0 [amdgpu] amdgpu_dpm_enable_vce+0x2e/0xc0 [amdgpu] vce_v4_0_hw_fini+0x95/0xa0 [amdgpu] amdgpu_device_fini_hw+0x232/0x30d [amdgpu] amdgpu_driver_unload_kms+0x5c/0x80 [amdgpu] amdgpu_pci_remove+0x27/0x40 [amdgpu] pci_device_remove+0x3e/0xb0 device_release_driver_internal+0x103/0x1d0 device_release_driver+0x12/0x20 pci_stop_bus_device+0x79/0xa0 pci_stop_and_remove_bus_device_locked+0x1b/0x30 remove_store+0x7b/0x90 dev_attr_store+0x17/0x30 sysfs_kf_write+0x4b/0x60 kernfs_fop_write_iter+0x151/0x1e0 Why: VCE/UVD had dependency on SMC block for their suspend but SMC block is the first to do HW fini due to some constraints How: Since the original patch was dealing with suspend issues move the SMC block dependency back into suspend hooks as was done in V1 of the original patches. Keep flushing idle work both in suspend and HW fini seuqnces since it's essential in both cases. Fixes: 859e4659273f1d ("drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend") Fixes: bf756fb833cbe8 ("drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend") Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
080e613c |
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27-Aug-2021 |
Satyajit Sahu <satyajit.sahu@amd.com> |
drm/amdgpu/vce: set the priority for each ring VCE has multiple rings. Set the proper priority level for each ring while initializing. Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bf756fb8 |
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17-Aug-2021 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend Perform proper cleanups on UVD/VCE suspend: powergate enablement, clockgating enablement and dpm disablement. This can fix some hangs observed on suspending when UVD/VCE still using(e.g. issue "pm-suspend" when video is still playing). Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c107171b |
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02-Feb-2021 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add the sched_score to amdgpu_ring_init Allow separate ring to share the same scheduler score. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1c6d567b |
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01-Apr-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: rework sched_list generation Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a9d4fe2f |
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20-Jan-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: remove unnecessary conversion to bool Better clean that up before some automation starts to complain about it Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47b757fb |
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09-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/amd: drop use of drmP.h in remaining files With this commit drm/amd/ has no longer any uses of the deprecated drmP.h header file. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-11-sam@ravnborg.org
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#
f61334b5 |
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08-May-2019 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu/VCE: set no_user_fence flag to true There is no user fence support for VCE Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4c905ec |
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18-Jan-2019 |
Jack Xiao <Jack.Xiao@amd.com> |
drm/amdgpu: add flags to emit_ib interface v2 Replace the last bool type parameter with a general flags parameter, to make the last parameter be able to contain more information. v2: drop setting need_ctx_switch = false Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0a46fc2e |
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20-Nov-2018 |
Brajeswar Ghosh <brajeswar.linux@gmail.com> |
drm/amd/amdgpu/vce_v3_0.c: Remove duplicate header Remove gca/gfx_8_0_d.h which is included more than once Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Brajeswar Ghosh <brajeswar.linux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
34955e03 |
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23-Oct-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Modify the argument of emit_ib interface use the point of struct amdgpu_job as the function argument instand of vmid, so the other members of struct amdgpu_job can be visit in emit_ib function. v2: add a wrapper for getting the VMID add the job before the ib on the parameter list. v3: refine the wrapper name Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c66ed765 |
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19-Oct-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amdgpu: Retire amdgpu_ring.ready flag v4 Start using drm_gpu_scheduler.ready isntead. v3: Add helper function to run ring test and set sched.ready flag status accordingly, clean explicit sched.ready sets from the IP specific files. v4: Add kerneldoc and rebase. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1ffdeca6 |
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17-Sep-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move more defines into amdgpu_irq.h Everything that isn't related to the IH ring. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
20acbed4 |
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13-Aug-2018 |
Emily Deng <Emily.Deng@amd.com> |
drm/amdgpu/vce: VCE entity initialization relies on ring initializtion Entity init should after ring init, as the entity's sched_rq's initialization is in ring init. SWDEV-161495 Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
091aec0b |
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25-May-2018 |
Andrey Grodzovsky <andrey.grodzovsky@amd.com> |
drm/amd: Use newly added interrupt source defs for VI v3. v2: Rebase v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5d4af988 |
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24-Jun-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vce: simplify vce instance setup Set the me instance in early init and use that rather than calculating the instance based on the ring pointer. Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3413accb |
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27-Jun-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix swapped emit_ib_size in vce3 The phys and vm versions had the values swapped. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0859df22 |
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27-Jun-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix swapped emit_ib_size in vce3 The phys and vm versions had the values swapped. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a7712897 |
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09-Nov-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: add VEGAM to VCE harvest config Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
08ebb6e9 |
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10-Apr-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Add APU support in vi_set_vce_clocks 1. fix set vce clocks failed on Cz/St which lead 1s delay when boot up. 2. remove the workaround in vce_v3_0.c Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Shirish S <shirish.s@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
c633c00b |
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04-Feb-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: separate PASID mapping from VM flush v2 Stuffing the PASID mapping into the VM flush isn't flexible enough since the PASID mapping changes not as often as we need a VM flush. v2: add missing use of gmc_v7_0_emit_pasid_mapping Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5a4633c4 |
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08-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: forward pasid to backend flush implementations rd the pasid from the VM code to the emit_vm_flush function and update all implementations with the new parameter. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4f46f22 |
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18-Dec-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: rename vm_id to vmid sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
32bec2af |
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31-Oct-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: allow harvesting check for Polaris VCE Fixes init failures on Polaris cards with harvested VCE blocks. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
1410f646 |
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29-May-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: Program ring for vce instance 1 at its register space We need program ring buffer on instance 1 register space domain, when only if instance 1 available, with two instances or instance 0, and we need only program instance 0 regsiter space domain for ring. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
45cc6586 |
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29-May-2017 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: Program ring for vce instance 1 at its register space We need program ring buffer on instance 1 register space domain, when only if instance 1 available, with two instances or instance 0, and we need only program instance 0 regsiter space domain for ring. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
50237287 |
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30-Mar-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: various cleanups for uvd/vce. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1c622002 |
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17-Mar-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amd/powerplay: add a new register define for APU in VI. the ixcurrent_pg_status addr is different between APU and DGPU. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
26679899 |
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13-Mar-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: refine vce_3.0 code. fix logic error in hw_fini and set_clockgating_state functions. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7ccf5aa8 |
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29-Nov-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/ih: store the full context id The contextID field (formerly known as src_data) of the IH vector stores client specific information about an interrupt. It was expanded from 32 bits to 128 on newer asics. Expand the src_id field to handle this. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d766e6a3 |
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29-Mar-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: switch ih handling to two levels (v3) Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
536fbf94 |
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11-Mar-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: change wptr to 64 bits (v2) Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
254cd2e0 |
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08-Feb-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: read hw register to check pg status. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d50e5c24 |
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09-Feb-2017 |
Alan Harrison <Alan.Harrison@amd.com> |
drm/amdgpu: Add to initialization of mmVCE_VCPU_CNTL register Add a bit needed during initialization into the driver, where it is supposed to be. Currently, this is happening in the VCE firmware, and although functional, this is the correct place to perform this initialization. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alan Harrison <Alan.Harrison@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6fc11b0e |
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25-Jan-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: refine vce3.0 code and related powerplay pg code. 1. not start vce3.0 when hw_init 2. stop vce3.0 when vce idle. 3. pg mask used to ctrl power down/up vce. 4. change cg pg sequence in powerplay. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
714b1f53 |
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10-Jan-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: refine vce3.0 initialize. 1. disable vce cg when vce hw initialize. 2. initizlize vce clock to 10KHz fo dgpu, so no need to set bypass clock to vce. Change-Id: I934c2c4820cc95c1bfa2fa41ff0f40a0d3cd1c40 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c79b5561 |
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05-Jan-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add get clockgating_state method for vce v3 Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
50a1ebc7 |
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10-Jan-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: fix program vce instance logic error. need to clear bit31-29 in GRBM_GFX_INDEX, then the program can be valid. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e05208de |
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10-Jan-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: fix bug set incorrect value to vce register Set the proper bits for clockgating setup. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c4642a47 |
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14-Dec-2016 |
Junwei Zhang <Jerry.Zhang@amd.com> |
drm/amd/amdgpu: add Polaris12 support (v3) v2: agd: squash in various fixes v3: agd: squash in: drm/amdgpu: remove unnecessary smc sk firmware for polaris12 Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ecc2cf7c |
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17-Nov-2016 |
Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> |
drm/amdgpu: enable VCE clockgating in Polaris-10/11 VCE clocks are set to be disabled, when not in use. Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
98614701 |
|
10-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add VCE VM session tracking Fix the problems with killing VCE sessions in VM mode. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a1255107 |
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13-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework IP block registration (v2) This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
79887142 |
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05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move align_mask and nop into ring funcs as well (v2) They are constant as well. v2: update uvd and vce phys ring structures as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
21cd942e |
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05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move the ring type into the funcs structure (v2) It's constant, so it doesn't make to much sense to keep it with the variable data. v2: update vce and uvd phys mode ring structures as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e12f3d7a |
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05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move IB and frame size directly into the engine description I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7bc6be82 |
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05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove explicit NULL init for parse_cs sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c That's just a leftover from radeon. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ef6239e0 |
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25-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vce3: only enable 3 rings on new enough firmware (v2) Older firmware versions don't support 3 rings. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=98016 v2: use define for fw version Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
da146d3b |
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13-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix amdgpu_need_full_reset (v2) IP types are not an index. Each asic may have number and type of IPs. Properly check the the type rather than using the type id as an index. v2: fix all the IPs to not use IP type as an idx as well. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
3374dceb |
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24-Sep-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: bypass vce clock if vce is idle on Fiji. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
58fafbaf |
|
16-Sep-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vce3: add ring callbacks for ib and dma frame size Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ea4a8c1d |
|
30-Aug-2016 |
Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> |
drm/amdgpu: add VCE VM mode support This adds VCE VM mode support from Stoney onwards. Session tracking is an open issue, yet to be supported. v2: Fixed warnings from checkpatch.pl Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c04399f1 |
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18-Aug-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: add vce bypass mode for tonga. fix issue that encode test failed on the second time when vce dpm enabled on tonga. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0174df4e |
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17-Aug-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: refine function name for consistency Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6f0359ff |
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24-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vce3: add support for third vce ring Not of much use at the moment (we don't really use the second ring either), but may be useful later. Reviewed-by: JimQu <Jim.Qu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
75c65480 |
|
24-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: track the number of vce rings Rather than using a hardcoded value. This allows different versions to expose more or less rings. No functional change. Reviewed-by: JimQu <Jim.Qu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9aeb774c |
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11-Aug-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: add mutex in check_soft for VCE v3 Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f3f0ea95 |
|
11-Aug-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Cleanup register access in VCE v3 Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bde1d8b2 |
|
03-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: enable VCE soft reset Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ac8e3f30 |
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03-Aug-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: remove RB1_BUSY bit checking This is a workaround to let VCE soft reset work. RB1_BUSY bit is always set, so remove its checking now, and we will depend on RB0_BUSY currently. After we find the root cause of RB1_BUSY, we can add it back. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9c0171b4 |
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03-Aug-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: fix harvest config checking in vce3 check_soft_reset Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
13d58d2a |
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03-Aug-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Don't set VCE CG in startup It's handled by DPM/PP properly. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6f906814 |
|
03-Aug-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Fix VCE CG order and resume defaults CG was being enabled in reverse sense from dpm/powerplay. Also fix the default CLK_EN signal to enable all of the blocks. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f16fe6d3 |
|
03-Aug-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: fix indentation in vce3 CG Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
115933a5 |
|
18-Jul-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: implement vce3 check/post_soft_reset Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ebff485e |
|
20-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use begin/end_use for VCE power/clock gating This fixes turning power and clock on when it is actually needed. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ec38f188 |
|
18-Jul-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: add bypass mode for vce3.0 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b7e2e9f7 |
|
19-Jul-2016 |
jimqu <Jim.Qu@amd.com> |
drm/amdgpu: correct coding style Signed-off-by: JimQu <Jim.Qu@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
567e6e29 |
|
15-Jul-2016 |
jimqu <Jim.Qu@amd.com> |
drm/amdgpu: S3 resume fail on Polaris10 Sometimes, driver can not return from fence waiting when doing VCE ring ib test. The issue is a asic special and random issue. so adjust VCE suspend and resume sequence. Signed-off-by: JimQu <Jim.Qu@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
88a907d6 |
|
04-May-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add name field to amd_ip_funcs (v2) Add name that we can print out in kernel messages to aid in debugging. v2: drop DAL changes for upstream Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
edf600da |
|
03-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amd: cleanup remaining spaces and tabs v2 This is the result of running the following commands: find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/[ \t]\+$//' {} \; find drivers/gpu/drm/amd/ -name "*.h" -exec sed -i 's/ \+\t/\t/' {} \; find drivers/gpu/drm/amd/ -name "*.c" -exec sed -i 's/ \+\t/\t/' {} \; v2: drop changes to DAL and internal headers Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
16a7989a |
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28-Mar-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Drop print_status callbacks. First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the moment anyway. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2cc0c0b5 |
|
14-Mar-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: change ELM/BAF to Polaris10/Polaris11 Adjust to preferred code names. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1b4eeea5 |
|
11-Mar-2016 |
Sonny Jiang <sonny.jiang@amd.com> |
drm/amdgpu: add VCE support to ELM/BAF Ellesmere and Baffin are VCE 3.4 Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a3f1cf35 |
|
12-Apr-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use max_dw in ring_init Instead of specifying the total ring size calculate that from the maximum number of dw a submission can have and the number of concurrent submissions. This fixes UVD with 8 concurrent submissions or more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9e5d5309 |
|
30-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: make pad_ib a ring function v3 The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making pad_ib a ring function v3: fix typo in macro name Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ea5e4c87 |
|
15-Jan-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: remove some more semaphore leftovers No longer needed since semaphores were removed. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2f4b9400 |
|
14-Jan-2016 |
Chunming Zhou <David1.Zhou@amd.com> |
drm/amdgpu: clean up hw semaphore support in driver No longer used. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e3b04bc7 |
|
05-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drma/dmgpu: move cg and pg flags into shared headers So they can be used by powerplay. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
808a934f |
|
04-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: handle vce pg flags properly Don't attempt to start/stop the vce block if pg is disabled. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
691ca86a |
|
15-Dec-2015 |
Tom St Denis <tom.stdenis@amd.com> |
amdgpu/vce3: Simplify vce_v3_0_hw_init and ensure both rings default to not ready. Simplified the ring test and added logic to ensure rings are marked not ready by default. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
74af1276 |
|
04-Jan-2016 |
Tom St Denis <tom.stdenis@amd.com> |
amdgpu/vce3: Remove magic constants from harvest register masks. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
81da2ede |
|
15-Dec-2015 |
Tom St Denis <tom.stdenis@amd.com> |
amdgpu/vce3: Simplify vce_v3_0_process_interrupt() Fold two cases into one for a LOC reduction. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
af18b0f7 |
|
15-Dec-2015 |
Tom St Denis <tom.stdenis@amd.com> |
amdgpu/vce3: Simplify vce_v3_0_soft_reset() LOC reduction and simplification. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
92988e60 |
|
15-Dec-2015 |
Tom St Denis <tom.stdenis@amd.com> |
amdgpu/vce3: Simplify idle and wait for idle code More LOC reductions in VCE3 code. This patch simplifies the is_idle and wait_for_idle logic. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
1dab5f06 |
|
15-Dec-2015 |
Tom St Denis <tom.stdenis@amd.com> |
amdgpu/vce3: Cleanup harvest config function. Basic LOC reduction. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
|
#
0689a570 |
|
23-Nov-2015 |
Eric Huang <JinHuiEric.Huang@amd.com> |
drm/amd/amdgpu: add vce3.0 clock gating support. (v2) v2: fix grbm locking Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
|
#
3c0ff9f1 |
|
17-Nov-2015 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: vce use multiple cache surface starting from stoney Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d6c29c30 |
|
17-Nov-2015 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: reset vce trap interrupt flag Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cfaba566 |
|
08-Oct-2015 |
Samuel Li <samuel.li@amd.com> |
drm/amdgpu: add VCE support for Stoney (v2) Stoney is VCE 3.x single. v2: Stoney is single pipe like Fiji Signed-off-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b7e4dad3 |
|
01-Sep-2015 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove old lockup detection infrastructure It didn't worked to well anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
|
#
be4f38e2 |
|
03-Sep-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix vce3 instance handling Need to properly handle the instances for the idle checks and soft reset. Acked-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
edff0e28 |
|
31-Aug-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: add insert_nop ring func and default implementation The insert_nop function is added to amdgpu_ring_funcs structure as well as the default implementation Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
188a9bcd |
|
27-Jul-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add support for VCE 3.x on Fiji VCE on fiji is single pipe only. Reviewed-by: David Zhang <david1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2f7d10b3 |
|
21-Jul-2015 |
Jammy Zhou <Jammy.Zhou@amd.com> |
drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2) Make the definitions common for all driver components v2: fix kfd Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6a585777 |
|
10-Jul-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: implement VCE 3.0 harvesting support (v4) For boards with bad VCE blocks, only configure the working block. v2: use the harvest info for pipe setup v3: fix mask check as noted by Leo v4: add dGPU support Reviewed-by: Christian König <christian.koenig@amd.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5fc3aeeb |
|
22-May-2015 |
yanyang1 <young.yang@amd.com> |
drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2) The structure is renamed and moved to amd_shared.h to make the component independent. This makes it easier to add new components in the future. v2: fix include path Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5bbc553a |
|
06-May-2015 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: implement VCE two instances support VCE 3.0 has two indentical instances in the engine, they share the same registers name in differrent memory block distinguished by the grbm_gfx_index, we set to master instance after init, it will dispatch task to slave instance. These two instances will share the same firmware, but have their own stacks and heaps. v2: add mutex for using grbm_gfx_index Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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e9822622 |
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06-May-2015 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: recalculate VCE firmware BO size Firmware required BO size changes in terms of ASIC family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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aaa36a97 |
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20-Apr-2015 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: Add initial VI support This adds initial support for VI asics. This includes Iceland, Tonga, and Carrizo. Our inital focus as been Carrizo, so there are still gaps in support for Tonga and Iceland, notably power management. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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