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0fdebc5e |
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07-Jun-2022 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 1) Based on the normalized pattern: this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1d93ba2a |
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26-Nov-2015 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: tauros2: use descriptive definitions for register bits Use descriptive definitions for the Tauros2 register bits, and while we're here, clean up the "Tauros2: %s line fill burt8." message. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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172f3fcb |
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26-Nov-2015 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: l2c: tauros2: fix OF-enabled non-DT boot Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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4ed89f22 |
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28-Oct-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: convert printk(KERN_* to pr_* Convert many (but not all) printk(KERN_* to pr_* to simplify the code. We take the opportunity to join some printk lines together so we don't split the message across several lines, and we also add a few levels to some messages which were previously missing them. Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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027f3f96 |
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11-Mar-2014 |
Arnd Bergmann <arnd@arndb.de> |
ARM: cache-tauros2: remove ARMv6 code When building a kernel with support for both ARMv6 and ARMv7 but no MMU, the call from tauros2_internal_init to adjust_cr causes a link error. While that could probably be resolved, we don't actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU implementations support both ARMv6 and ARMv7 and we already assume that we are using them only in ARMv7 mode. Removing the ARMv6 code path reduces the code size and avoids the linker error. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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c2b7e05c |
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31-Jul-2012 |
Chao Xie <xiechao.mail@gmail.com> |
ARM: cache: add dt support for tauros2 cache Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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38f2e377 |
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31-Jul-2012 |
Chao Xie <xiechao.mail@gmail.com> |
ARM: cache: add extra feature enable for tauros2 The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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fa79b8d6 |
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31-Jul-2012 |
Chao Xie <xiechao.mail@gmail.com> |
ARM: cache: add cputype.h for tauros2 Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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5967b546 |
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31-Jul-2012 |
Chao Xie <xiechao.mail@gmail.com> |
ARM: cache: fix uninitialized ptr in tauros2_init init the variable "mode" to NULL to ensure the later NULL checking is taking effect. Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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89326f76 |
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06-May-2012 |
Chao Xie <chao.xie@marvell.com> |
ARM: cache: tauros2: add disable and resume callback For the SOC chips using tauros2 cache, will need disable and resume tauros2 cache for SOC suspend/resume. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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15d07dc9 |
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28-Mar-2012 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: move CP15 definitions to separate header file Avoid namespace conflicts with drivers over the CP15 definitions by moving CP15 related prototypes and definitions to a private header file. Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> [Tegra] Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> [EP93xx] Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: David Howells <dhowells@redhat.com>
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195864cf |
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19-Jan-2012 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: move CP15 definitions to separate header file Avoid namespace conflicts with drivers over the CP15 definitions by moving CP15 related prototypes and definitions to a private header file. Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> [Tegra] Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> [EP93xx] Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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573a652f |
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24-Nov-2009 |
Lennert Buytenhek <buytenh@marvell.com> |
ARM: Add Tauros2 L2 cache controller support Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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