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031beb4e |
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16-Aug-2023 |
Warner Losh <imp@FreeBSD.org> |
sys: Remove $FreeBSD$: one-line sh pattern Remove /^\s*#[#!]?\s*\$FreeBSD\$.*$\n/
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c32b6c74 |
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25-Apr-2023 |
Mitchell Horne <mhorne@FreeBSD.org> |
riscv: retire the FPE kernel option We always build the kernel floating point support. Now that the riscv64sf userspace variant has been removed the option is required for correct operation. Reviewed by: jhb Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D39851
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91dc225a |
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20-Oct-2022 |
Warner Losh <imp@FreeBSD.org> |
conf: Document why we have ARM64 and RISCV options These are needed for the 'cpu ARM64' and 'cpu RISCV' options in these architecture's config files. cpu lines are non-optional in config(8), so we must define them here. There's no other use for them in the tree. Sponsored by: Netflix
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2d53a67c |
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12-Jun-2018 |
Ruslan Bukin <br@FreeBSD.org> |
o Add driver for PLIC (Platform-Level Interrupt Controller) device. o Convert interrupt machdep support to use INTRNG code. Sponsored by: DARPA, AFRL
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7804dd52 |
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16-Nov-2016 |
Ruslan Bukin <br@FreeBSD.org> |
Add full softfloat and hardfloat support for RISC-V. Hardfloat is now default (use riscv64sf as TARGET_ARCH for softfloat). Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D8529
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f8f69c93 |
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25-Apr-2016 |
Ruslan Bukin <br@FreeBSD.org> |
Revert r298477 ("Clear the DDR memory"). There is no need to clear all the DDR memory (we only need to clear BSS section). I was playing with non-default version of hardware (the bitfile synthesized for 4-level page memory system) and clearing was helpful, but then realized support for 4-level page system is untested/broken in both RocketCore and lowRISC.
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ce2b4fcf |
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22-Apr-2016 |
Ruslan Bukin <br@FreeBSD.org> |
Clear the DDR memory. This should be done by bootloaders, but they have no such feature yet. This fixes operation on Rocket Core and lowRISC.
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28029b68 |
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29-Jan-2016 |
Ruslan Bukin <br@FreeBSD.org> |
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
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