sys: Automated cleanup of cdefs and other formatting

Apply the following automated changes to try to eliminate
no-longer-needed sys/cdefs.h includes as well as now-empty
blank lines in a row.

Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/
Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/
Remove /\n+#if.*\n#endif.*\n+/
Remove /^#if.*\n#endif.*\n/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/

Sponsored by: Netflix

sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

arm64/disassem.c: add extended register instruction definitions

Add disassembly support for the following extended register
instructions: add, adds, sub, subs, cmp, cmn.

Reviewed by: mhorne
MFC after: 1 week
Pull Request: https://reviews.freebsd.org/D40967

arm64/disassem.c: remove redundant OP_RN_SP for TYPE_02

Removed redundant OP_RN_SP for TYPE_02, since these addressing modes
always use the SP register, never XZR.

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D40588

arm64/disassem.c: Add shifted register definitions with ror

Add disassembly support for the following shifted register instructions:
* mvn
* orn
* orr
* and
* ands
* bic
* bics
* eon
* eor
* tst

According to Arm64 documenation, operational pseuducode of shifted
register instruction must return `UNDEFINED` if shift type is `RESERVED`
('11'). Hence, removed "rsv" from `shift_2` array and add "ror". In case
of shift type is 3 and this type is `RESERVED`, we will return
`undefined`.

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D40386

arm64/disassem.c: Add shifted register instruction definitions

Add disassembly support for the following shifted register instructions:
* adds
* subs
* sub
* neg
* negs
* cmp
* cmn

The 'Mandatory Tokens' checks are relaxed to allow for the alias
instructions (e.g. cmp) which hard-code one or more registers as xzr.

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D40006

arm64/disassem.c: Make output lowercase

Update the few uppercase fields fields to be consistent with others.

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D39820

arm64/disassem.c: Add detection of xzr and sp

Added support to distinguish between XZR/WZR and SP/WSP registers.

Add new OP_ flags to indicate if the instruction allows the use of SP
for a given register field. "wSP" and "SP" are removed from w_reg and
x_reg, and helper functions are introduced for this purpose of detecting
the correct name of the x31 register.

mhorne: While here, adjust some whitespace issues from a previous
commit.

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D39862

arm64/disassem.c: Add support str/strb/strh instructions

Added disassembly support for each type of str/strb/strh instruction
encoding.

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D39336

arm64/disassem.c: Fix typo sxts to sxts and amount for TYPE_02

The current implementation is wrong, since it unconditionally sets the
amount equal to the <size> field of the instruction. However, when the
<S> bit (scale) is not set, it must be zero.

Also fix a typo, sxts to sxtx, according to the Arm64 documentation.

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D39334

arm64/disassem.c: style and formatting

Reviewed by: mhorne
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D38899

ARM64 disassembler: support for LDR instructions

Implemented disassembly for a whole bunch of
various ldr instructions.

Obtained from: Semihalf
Sponsored by: Cavium
Approved by: cognet (mentor)
Reviewed by: zbb
Differential revision: https://reviews.freebsd.org/D5217

Framework for ARM64 instruction disassembler

Provide an easy to use framework for ARM64 DDB disassembler.
This commit does not contain full list of instruction opcodes.

Obtained from: Semihalf
Sponsored by: Cavium
Approved by: cognet (mentor)
Reviewed by: zbb, andrew, cognet
Differential revision: https://reviews.freebsd.org/D5114