Revert r330897:

This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.

Revert with prejudice.

This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.

Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.

Requested by: gjb (re)

Partial merge of the SPDX changes

These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.

No objections from: pfg

Partial MFC r303693:

Merge MPC85XX and QorIQ config options

Only a partial MFC, keeping files.powerpc and options.powerpc intact, to
retain compatibility with any kernel configs that may use the QORIQ_DPAA option.

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Allow the size argument for law_enable() to be non-power-of-2.

Although the local access windows are powers of 2 in size, allow arguments that
aren't power of 2, and round up.

Add platform support for QorIQ SoCs.

This includes the following changes:
* SMP kickoff for QorIQ (tested on P5020)
* Errata fixes for some silicon revisions
* Enables L2 (and L3 if available) caches
Obtained from: Semihalf
Sponsored by: Alex Perez/Inertial Computing

Add support for new LAW registers in QorIQ SoCs.

QorIQ SoCs (e5500 core, P5 family) have 2 BARs for local access windows, while
MPC85XX, and P1/P2 families use only a single BAR register.

This also adds the QORIQ_DPAA option, mutually exclusive to MPC85XX, to handle
this difference.

Obtained from: Semihalf
Sponsored by: Alex Perez/Inertial Computing

Interrelated improvements to early boot mappings:
- Remove explicit requirement that the SOC registers be found except as an
optimization (although the MPC85XX LAW drivers still require they be found
externally, which should change).
- Remove magic CCSRBAR_VA value.
- Allow bus_machdep.c's early-boot code to handle non 1:1 mappings and
systems not in real-mode or global 1:1 maps in early boot.
- Allow pmap_mapdev() on Book-E to reissue previous addresses if the
area is already mapped. Additionally have it check all mappings, not
just the CCSR area.

This allows the console on e500 systems to actually work on systems where
the boot loader was not kind enough to set up a 1:1 mapping before starting
the kernel.

Just return if the size of the window is 0. This can happen when the
FDT does not define all ranges possible for a particular node (e.g.
PCI).
While here, only update the trgt_mem and trgt_io pointers if there's
no error. This avoids that we knowingly write an invalid target (= -1).

Fix missing header for powerpc_iomb().

Pointy hat to: me

Replace eieio; sync for creating bus-space memory barriers with sync.
sync performs a strict superset of the functions of eieio, so using both
is redundant. While here, expand bus barriers to all bus_space operations,
since many drivers do not correctly use bus_space_barrier().

In principle, we can also replace sync just with eieio, for a significant
performance increase, but it remains to be seen whether any poorly-written
drivers currently depend on the side effects of sync to properly function.

MFC after: 1 week

o Determine the number of LAWs in a way the is future proof. Only the
MPC8555(E) has 8 LAWs, so don't make that the default case. Current
processors have 12 LAWs so use that as the default instead.
o Determine the target ID of the PCI/PCI-X and PCI-E controllers in
a way that's more future proof. There's almost a perfect mapping
from HC register offset to target ID, so use that as the default.
Handle the MPC8548(E) specially, since it has a non-standard target
ID for the PCI-E controller. Don't worry about whether the processor
implements the target ID here, because we should not get called for
PCI/PCI-X or PCI-E host controllers that don't exist.

Restructure how reset and poweroff are handled on PowerPC systems, since
the existing code was very platform specific, and broken for SMP systems
trying to reboot from KDB.

- Add a new PLATFORM_RESET() method to the platform KOBJ interface, and
migrate existing reset functions into platform modules.
- Modify the OF_reboot() routine to submit the request by hand to avoid
the IPIs involved in the regular openfirmware() routine. This fixes
reboot from KDB on SMP machines.
- Move non-KDB reset and poweroff functions on the Powermac platform
into the relevant power control drivers (cuda, pmu, smu), instead of
using them through the Open Firmware backdoor.
- Rename platform_chrp to platform_powermac since it has become
increasingly Powermac specific. When we gain support for IBM systems,
we will grow a new platform_chrp.

Convert Freescale PowerPC platforms to FDT convention.

The following systems are affected:

- MPC8555CDS
- MPC8572DS

This overhaul covers the following major changes:

- All integrated peripherals drivers for Freescale MPC85XX SoC, which are
currently in the FreeBSD source tree are reworked and adjusted so they
derive config data out of the device tree blob (instead of hard coded /
tabelarized values).

- This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC,
QUICC, UART, CFI.

- Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire
ocpbus(4) driver, which was based on hard-coded config data.

Note that world for these platforms has to be built WITH_FDT.

Reviewed by: imp
Sponsored by: The FreeBSD Foundation

Make MPC85xx LAW handling and reset routines aware of the MPC8548 variant.

Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@.

Extend and improve MPC85XX Local Bus management.

- Make LBC resources management self-contained: introduce explicit LBC
resources definition (much like the OCP), provide dedicated rman for LB mem
space.

- Full configuration of an LB chip select device: program LAW and BR/OR, map
into KVA, handle all LB attributes (bus width, machine select, ecc,
write protect etc).

- Factor out LAW manipulation routines into shared code, adjust OCP area
accordingly.

- Other LBC fixes and clean-ups.

Obtained from: Semihalf

Improve MPC85XX helper routines.

- Move CCSR accessors to the shared MPC85XX area
- Simplify SVR version subfield handling
- Adjust OCP

Remove mfsvr():
o The function is defined unconditionally but depends on SPR_SVR,
which is defined conditionally.
o spr.h defines mfspr() and mtspr(), which is no worse to use.

Use RSTCR for resetting the MPC8572 (the old way does not apply).

Obtained from: Freescale, Semihalf

Introduce a dedicated file for MPC85xx-specific routines. Move cpu_reset()
there, as it's not relevant to Book-E specification, but is an implementation
detail, directly dependent on the given SoC version.