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272461 |
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02-Oct-2014 |
gjb |
Copy stable/10@r272459 to releng/10.1 as part of the 10.1-RELEASE process.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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270075 |
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16-Aug-2014 |
ian |
MFC r269594, r269596, r269597, r269598, r269605, r269606:
Set ofwbus and simplebus to attach during BUS_PASS_BUS.
Define names that drivers can use to adjust their position relative to other drivers within a BUS_PASS
Adjust ofwbus and simplebus to attach at BUS_PASS_ORDER_MIDDLE, so that a platform can attach some other bus first if necessary.
Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.
Attach arm generic interrupt and timer drivers in the middle of BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively.
Add an arm option, ARM_DEVICE_MULTIPASS, used to opt-in to multi-pass device attachment on arm platforms. If this is defined, nexus attaches early in BUS_PASS_BUS, and other busses and devices attach later, in the pass number they are set up for. Without it defined, nexus attaches in BUS_PASS_DEFAULT and thus so does everything else, which is status quo.
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266387 |
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17-May-2014 |
ian |
MFC 265861, 265870:
Make the hardware memory and instruction barrier functions work on armv4 and armv5 as well.
Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
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266384 |
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17-May-2014 |
ian |
MFC 265440, 265441, 265444, 265445, 265446, 265447:
Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor style(9) nits. Use DEVMETHOD_END.
Break out the code that figures out the L2 cache geometry to its own routine, so that it can be called from multiple places in upcoming changes.
Call platform_pl310_init() before enabling the controller, and handle the case where the controller is already enabled.
Add defines for the bits in the PL310 debug control register.
Add a public routine to set the L2 cache ram latencies. This can be called by platform init routines to fine-tune cache performance.
Enable PL310 power-saving modes and tune the cache ram latencies for imx6.
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266375 |
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17-May-2014 |
ian |
MFC 265035: Move duplicated code to print l2 config into the common code.
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266152 |
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15-May-2014 |
ian |
MFC r261410
Follow r261352 by updating all drivers which are children of simplebus to check the status property in their probe routines.
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259313 |
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13-Dec-2013 |
ian |
MFC r256647:
Invalidate the entire L2 cache before enabling it. Say whether it has been enabled or disabled.
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256281 |
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10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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253788 |
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29-Jul-2013 |
cognet |
The errata 727915 requires a different workaround for r2p0, we have to explicitely clean/invalidate every cache line using way/set operations.
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245192 |
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08-Jan-2013 |
cognet |
Remove old declarations.
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245120 |
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07-Jan-2013 |
gonzo |
Release version check for erratum 727915 workaround in l2_wbinv_range function implementation causes function fail to flush caches for chip with RTL number 0x7. I failed to find official PL310 revision with this RTL number so further research on this matter required.
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245087 |
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05-Jan-2013 |
andrew |
Fix the build:
* Use pl310_softc when the softc is otherwise unavailable. * Use the correct spelling of sc_rtl_revision.
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245083 |
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05-Jan-2013 |
andrew |
Only work around errata when we are on a part where the erratum applies.
Reviewed by: gonzo
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244914 |
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31-Dec-2012 |
gonzo |
PL310 driver update:
- Add pl310.disable tunable to disable L2 cache altogether. In order to make sure that it's 100% disabled we use cache event counters for cache line eviction and read allocate events and panic if any of these counters increased. This is purely for debugging purpose - Direct access DEBUG_CTRL and CTRL might be unavailable in unsecure mode, so use platform-specific functions for these registers - Replace #if 1 with proper erratum numbers - Add erratum 753970 workaround - Remove wait function for atomic operations - Protect cache operations with spin mutex in order to prevent race condition - Disable instruction cache prefetch and make sure data cache prefetch is enabled in OMAP4-specific intialization
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243359 |
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20-Nov-2012 |
cognet |
Make sure the address starts on a cache line boundary.
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239268 |
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15-Aug-2012 |
gonzo |
Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
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