Copy stable/10@r272459 to releng/10.1 as part of
the 10.1-RELEASE process.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

MFC r269390: Fix unwind info in hand-written asm (avoid nested functions).

MFC 265694, 265705, 265784:

Move the mptramp code which is specific to the Marvell ArmadaXP SoC out of
the common locore.S file and into the mv/armadaxp directory.

Consolidate all the AP core startup stuff under a single #ifdef SMP block

Call idcache_inv_all from the AP core entry code before turning on the MMU.
Also, enable instruction and branch caches, which should be safe now that
they're properly initialized/invalidated first.

MFC 265023, 265024, 265036:

There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so
map them both to the same interrupt number like other arches do.

Flush and invalidate caches on each CPU as part of handling IPI_STOP.

Don't use multiprocessing-extensions instruction on processors that don't
support SMP.

MFC 264990, 264994, 265020, 265025:

Call cpu_icache_sync_range() rather than sync_all since we know the range
and flushing the entire icache is needlessly expensive.

Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).

Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed.

Explain why wbinv_all is SMP-safe when dumping, and add a missing l2 cache
flush. (Either it was missing here, or it isn't needed in the minidump
case. Adding it here seems like the safer path to consistancy.)

MFC 264128, 264129, 264130, 264135,

Fix TTB set operation for armv7. Perform sychronization (by "isb" barrier)
after TTB is set.

Fix TLB maintenance issues for armv6 and armv7.

- Add cpu_cpwait to comply with the convention.
- Add missing TLB invalidations, especially in pmap_kenter & pmap_kremove
with distinguishing between D and ID pages.
- Modify pmap init/bootstrap invalidations to ID, just to be safe.
- Fix TLB-inv and PTE_SYNC ordering.

Allocate per-cpu resources for doing pmap_zero_page() and pmap_copy_page().
This is performance enhancement rather than bugfix.

We don't support any ARM systems with an ISA bus and don't need a freelist
of memory to support ISA addressing limitations.

MFC 263250, 263251, 263424, 263425, 263426, 263427, 263430, 263431

Use the same cache terminology as the ARM docs in comments. No
functional changes.

Use armv7 TLB flush code, not arm11, for cortex-a processors.

Exynos/ Arndale...
- Disable debugging by default.
- Add display-related and clk devices to the tree
- Prevent resources intersection with EHCI driver
- Add display-related and clk devices to the tree
- Prevent resources intersection with EHCI driver
- Add driver for Display Controller.
- Add support for Samsung Chromebook (ARM Cortex A15 machine).
- Rename mct and ehci drivers files to match common naming.

MFC r262534, r262548, r262549, r262552, r262568, r262581, r262583, r262584,
r262585, r262587, r262696, r262712

Replace many pasted identical definitions of cpu_initclocks() with a common
implementation in arm/machdep.c.

aicasm: Don't complain about missing prototypes to ease bootstrap issues.

Vybrid: Add driver for Inter-Integrated Circuit (I2C).

imx6: Initialize the Low Power Mode bits to keep the ARM cores running
during WFI.

All our current ARM multi-core systems have all cores in one package with
a shared L2 cache, reflect that in the common cpu_topo() routine.

mpcore timer: Supply a DELAY() implementation via weak linkage, so that
SoC-specific code can supply a better implementation.

imx6: Add some rudimentary voltage control.

Add an armv7 implementation of cpu_sleep().

Add __used attribute so that the DELAY implementation doesn't get
optimized away as unreferenced, causing linker errors when trying to
resolve the weak reference to the missing function.

MFC r262409, r262411, r262413, r262420, r262426, r262427, r262440, r262456,
r262482, r262483, r262531,

Move the declaration for mpentry() into a header file instead of pasting
it into a bunch of different .c files.

If the L2 cache type is PIPT, pass a physical address for a flush.

Actually set the proper bit to indicate TTB shared memory.

Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support.

Invalidate caches immediately upon entry to init_secondary(). Also set
the Bufferable bit in the PDE entries of the secondary processor startup
pagetables.

Add the bits needed to run SMP on imx6.

Invalidate the SCU cache tag ram on all 4 cores, not just 1-3.

Minor tweaks to the imx GPT timer

Vybrid enhancements...
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock
- Add support for Quartz Module.
- Pin configuration is a complete iomux register now and includes
drive strength, pull mode, mux mode, speed, etc.
- Add i2c devices to the tree
- Add IPG clock

MFC r256707, r256708, r257291, r258358

Switch to use WBWA mappings for page tables on armv6, this is needed for SMP.
Fix PTE_SYNC() for PIPT L2 caches, using the virtual address wasn't so useful.
Use PTE_SYNC() for >= armv6
Spell cpu_l2cache_wb_range correctly.

Fix condition that determines PMAP_NEEDS_PTE_SYNC value for ARM

Use values of the correct defines to determine statement's result.
ARM_ARCH_ symbols are always defined, hence only values are relevant.

Avoid clearing EXEC permission bit when setting the page RW on ARMv6/v7

When emulating modified bit the executable attribute was cleared by
mistake when calling pmap_set_prot().

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Add an END macro to ARM. This is mostly used to tell gas where the bounds
of the functions are when creating the EABI unwind tables.

Use the "inner shareable" variations of flush/invalidate functions for SMP.

Submitted by: Giovanni Trematerra <gianni at freebsd DOT org>

Merging projects/armv6, part 1

Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms