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259065 |
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07-Dec-2013 |
gjb |
- Copy stable/10 (r259064) to releng/10.0 as part of the 10.0-RELEASE cycle. - Update __FreeBSD_version [1] - Set branch name to -RC1
[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so start releng/10.0 at '100' so the branch is started with a value ending in zero.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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256281 |
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10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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227628 |
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17-Nov-2011 |
nwhitehorn |
Use a global __pure2 function instead of a global register variable for curthread, like on x86 and sparc64. This makes the kernel somewhat more clang friendly, which doesn't support global register variables.
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223485 |
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23-Jun-2011 |
nwhitehorn |
Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64) instead of a PCPU field for curthread. This averts a race on SMP systems with a high interrupt rate where the thread looking up the value of curthread could be preempted and migrated between obtaining the PCPU pointer and reading the value of pc_curthread, resulting in curthread being observed to be the current thread on the thread's original CPU. This played merry havoc with the system, in particular with mutexes. Many thanks to jhb for helping me work this one out.
Note that Book-E is in principle susceptible to the same problem, but has not been modified yet due to lack of Book-E hardware.
MFC after: 2 weeks
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222618 |
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02-Jun-2011 |
nwhitehorn |
If running under a hypervisor, don't yell at the user about starting unknown CPU types, instead relying on the hypervisor to have given us a reasonable environment.
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215197 |
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12-Nov-2010 |
nwhitehorn |
Partially revert r215182. There appears to be a silicon bug on the 970 that causes AP bringup to fail if some of the Cell HID-register code is anywhere in the instruction stream. Pending a better solution, cache performance on SMP Cell systems running without a hypervisor will be suboptimal.
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215182 |
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12-Nov-2010 |
nwhitehorn |
Add CPU support code for the IBM Cell Broadband Engine.
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209975 |
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13-Jul-2010 |
nwhitehorn |
MFppc64:
Kernel sources for 64-bit PowerPC, along with build-system changes to keep 32-bit kernels compiling (build system changes for 64-bit kernels are coming later). Existing 32-bit PowerPC kernel configurations must be updated after this change to specify their architecture.
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209114 |
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12-Jun-2010 |
nwhitehorn |
Make SMP work on MPC7400-based Apple desktops like the PowerMac3,3.
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198427 |
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23-Oct-2009 |
nwhitehorn |
Add some more paranoia to setting HID registers, and update the AIM clock routines to work better with SMP. This makes SMP work fully and stably on an Xserve G5.
Obtained from: Book-E (clock bits)
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198378 |
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23-Oct-2009 |
nwhitehorn |
Add SMP support on U3-based G5 systems. This does not yet work perfectly: at least on my Xserve, getting the decrementer and timebase on APs to tick requires setting up a clock chip over I2C, which is not yet done.
While here, correct the 64-bit tlbie function to set the CPU to 64-bit mode correctly.
Hardware donated by: grehan
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192067 |
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13-May-2009 |
nwhitehorn |
Factor out platform dependent things unrelated to device drivers into a new platform module. These are probed in early boot, and have the responsibility of determining the layout of physical memory, determining the CPU timebase frequency, and handling the zoo of SMP mechanisms found on PowerPC.
Reviewed by: marcel, raj Book-E parts by: raj
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190681 |
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03-Apr-2009 |
nwhitehorn |
Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge mode provided, for example, on the PowerPC 970 (G5), as well as on related CPUs like the POWER3 and POWER4.
This also adds support for various built-in hardware found on Apple G5 hardware (e.g. the IBM CPC925 northbridge).
Reviewed by: grehan
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183090 |
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16-Sep-2008 |
marcel |
Rewrite cpudep_ap_bootstrap(). We now enable L3, L2, L1D and L1I caches if not yet enabed. This is required for coherency and atomic operations to work, not to mention performance. We use the L2 and L3 cache settings of the BSP to configure the APs caches. Can't be bad.
Program NAP and not DOZE. DOZE is present only on earlier CPUs and the bit is reserved on the MPC7441 & MPC7451. NAP will do bus snooping to keep caches coherent.
Program the PIR with the cpuid. This may not be necessary...
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183060 |
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15-Sep-2008 |
marcel |
Remove the tracing from the AP startup. The AP is known to start and the tracing can interfere with AP startup. Instead, use the available space in the reset vector for the initial stack.
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183030 |
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14-Sep-2008 |
marcel |
Dont worry about PSL_RI (restartable interrupt indicator) in common PowerPC code when all we want to achieve is to enable external interrupts. We can set PSL_RI at any time before we allow interrupts and/or exceptions, so move it to the AIM specific initialization and do it when we also set PSL_ME (machine check enable).
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178628 |
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27-Apr-2008 |
marcel |
MFp4: SMP support
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