- Copy stable/10 (r259064) to releng/10.0 as part of the
10.0-RELEASE cycle.
- Update __FreeBSD_version [1]
- Set branch name to -RC1

[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so
start releng/10.0 at '100' so the branch is started with
a value ending in zero.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Simplify check for CMPXCHG8B instruction. Note CMPXCHG8B instruction is
always available for Rise mP6 processors although it is not set by CPUID.

x86: detect mwait capabilities and extensions, when present

Reviewed by: kib (earlier amd64-only version)
MFC after: 2 weeks

Add SMP/i386 suspend/resume support.
Most part is merged from amd64.

- i386/acpica/acpi_wakecode.S
Replaced with amd64 code (from realmode to paging enabling code).

- i386/acpica/acpi_wakeup.c
Replaced with amd64 code (except for wakeup_pagetables stuff).

- i386/include/pcb.h
- i386/i386/genassym.c
Added PCB new members (CR0, CR2, CR4, DS, ED, FS, SS, GDT, IDT, LDT
and TR) needed for suspend/resume, not for context switch.

- i386/i386/swtch.s
Added suspendctx() and resumectx().
Note that savectx() was not changed and used for suspending (while
amd64 code uses it).
BSP and AP execute the same sequence, suspendctx(), acpi_wakecode()
and resumectx() for suspend/resume (in case of UP system also).

- i386/i386/apic_vector.s
Added cpususpend().

- i386/i386/mp_machdep.c
- i386/include/smp.h
Added cpususpend_handler().

- i386/include/apicvar.h
- kern/subr_smp.c
- sys/smp.h
Added IPI_SUSPEND and suspend_cpus().

- i386/i386/initcpu.c
- i386/i386/machdep.c
- i386/include/md_var.h
- pc98/pc98/machdep.c
Moved initializecpu() declarations to md_var.h.

MFC after: 3 days

Finally, try to enable the nxstacks on amd64 and powerpc64 for both 64bit
and 32bit ABIs. Also try to enable nxstacks for PAE/i386 when supported,
and some variants of powerpc32.

MFC after: 2 months (if ever)

Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta
CPUs. These CPUs need explicit MSR configuration to expose ceratin CPU
capabilities (e.g., CMPXCHG8B) to work around compatibility issues with
ancient software. Unfortunately, Rise mP6 does not set the CX8 bit in CPUID
and there is no MSR to expose the feature although all mP6 processors are
capable of CMPXCHG8B according to datasheets I found from the Net. Clean up
and simplify VIA PadLock detection while I am in the neighborhood.

specialreg.h: add AMD-specific "Hardware Configuration Register" MSR

It seems that this MSR has been available in a range of AMD processors
families for quite a while now.

Note1: not all AMD MSRs that are found in amd64 specialreg.h are also in
the i386 version.
Note2: perhaps some additional name component is needed to distinguish
AMD-specific MSRs.

MFC after: 5 days

Use 'saveintr' instead of 'savecrit' or 'eflags' to hold the state returned
by intr_disable().

Requested by: bde

Use intr_disable() and intr_restore() instead of frobbing the flags register
directly to disable interrupts.

Reviewed by: bde (earlier version)
MFC after: 2 weeks

Tweak the logic to disable CLFLUSH in virtual environments to work around
problems with flushing the local APIC register range so that it checks
vm_guest directly.

Reviewed by: kib, alc
MFC after: 2 weeks

- Style nits.
- Remove unneeded TUNABLE_INT().

Suggested by: avg, kib

- Add hw.clflush_disable loader tunable to avoid panic (trap 9) at
map_invalidate_cache_range() even if CPU is not Intel.
- This tunable can be set to -1 (default), 0 and 1. -1 is same as
current behavior, which automatically disable CLFLUSH on Intel CPUs
without CPUID_SS (should be occured on Xen only). You can specify 1
when this panic happened on non-Intel CPUs (such as AMD's). Because
disabling CLFLUSH may reduce performance, you can try with setting 0
on Intel CPUs without SS to use CLFLUSH feature.

Reviewed by: kib
Reported by: karl, kuriyama
Related to: kern/138863

As a workaround, for Intel CPUs, do not use CLFLUSH in
pmap_invalidate_cache_range() when self-snoop is apparently not reported
in cpu features. We get a reserved trap when clflushing APIC registers
window.

XEN in full system virtualization mode removes self-snoop from CPU
features, making this a problem.

Tested by: csjp
Reviewed by: alc
MFC after: 3 days

As was done in r195820 for amd64, use clflush for flushing cache lines
when memory page caching attributes changed, and CPU does not support
self-snoop, but implemented clflush, for i386.

Take care of possible mappings of the page by sf buffer by utilizing
the mapping for clflush, otherwise map the page transiently. Amd64
used direct map.

Proposed and reviewed by: alc
Approved by: re (kensmith)

Add basic i386 support for VIA Nano processors.

Replace more strcmp(cpu_vendor, "foo") with cpu_vendor_id.

Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").

Reviewed by: jhb, peter (early amd64 version)

Detect Advanced Power Management Information for AMD CPUs.

Support the VIA C7 Eden CPU and treat it just like a C7 Esther. We may
want to adjust this code to just assume that all CPUs >= Esther should
be checked for the extended cpuid flags register.

MFC after: 3 days
PR: i386/119491

Add the PG_NX support for i386/PAE.

Reviewed by: alc

Initialise (if necessary) the VIA C3/C7 features.
Store the capabilities for further use by random(4), padlock(4), ...

Obtained from: mostly OpenBSD
MFC after: 1 week

Use the method described in IA-32 Intel Architecture Software Developer's
Manual chapter 11.6.6 to get valid mxcsr bits, use the mxcsr mask to clear
invalid bits passed by user code.

Reviewed by: bde

- Print number of physical/logical cores and more CPUID info.
- Add newer CPUID definitions for future use.

Many thanks to Mike Tancsa <mike at sentex dot net> for providing test
cases for Intel Pentium D and AMD Athlon 64 X2.

Approved by: anholt (mentor)

Remove the CPU_ENABLE_SSE option from the i386 and pc98 architectures,
as they are already default for I686_CPU for almost 3 years, and
CPU_DISABLE_SSE always disables it. On the other hand, CPU_ENABLE_SSE
does not work for I486_CPU and I586_CPU.

This commit has:
- Removed the option from conf/options.*
- Removed the option and comments from MD NOTES files
- Simplified the CPU_ENABLE_SSE ifdef's so they don't
deal with CPU_ENABLE_SSE from kernel configuration. (*)

For most users, this commit should be largely no-op. If you used to
place CPU_ENABLE_SSE into your kernel configuration for some reason,
it is time to remove it.

(*) The ifdef's of CPU_ENABLE_SSE are not removed at this point, since
we need to change it to !defined(CPU_DISABLE_SSE) && defined(I686_CPU),
not just !defined(CPU_DISABLE_SSE), if we really want to do so.

Discussed on: -arch
Approved by: re (scottl)

Begin promoting the AMD-originated feature flags to first class flags, now
that newer Intel cpu hardware implements them too. This includes things
like the NX (pte no-execute) flag for execute protection. We'll need to
reference this for implementing no-exec in pmap.c at some point.

Some feature flags are duplicated in both the Intel-orignated bits and
the AMD bits. Suppress the the duplicates correctly - the old code
assumed they were a 1:1 mapping which is not correct. We can't just mask
off the bits present in cpu_feature.

Converge with amd64 where this originated from.

Intel cpu's that implement any AMD features will report them in dmesg now.

Approved by: re

Add the 2nd word of IA32 feature flags. This includes things such as SSE3.

Obtained from: sys/amd64/amd64/identcpu.

Update a comment.

Requested by: bde

New APIC support code:

- The apic interrupt entry points have been rewritten so that each entry
point can serve 32 different vectors. When the entry is executed, it
uses one of the 32-bit ISR registers to determine which vector in its
assigned range was triggered. Thus, the apic code can support 159
different interrupt vectors with only 5 entry points.
- We now always to disable the local APIC to work around an errata in
certain PPros and then re-enable it again if we decide to use the APICs
to route interrupts.
- We no longer map IO APICs or local APICs using special page table
entries. Instead, we just use pmap_mapdev(). We also no longer
export the virtual address of the local APIC as a global symbol to
the rest of the system, but only in local_apic.c. To aid this, the
APIC ID of each CPU is exported as a per-CPU variable.
- Interrupt sources are provided for each intpin on each IO APIC.
Currently, each source is given a unique interrupt vector meaning that
PCI interrupts are not shared on most machines with an I/O APIC.
That mapping for interrupt sources to interrupt vectors is up to the
APIC enumerator driver however.
- We no longer probe to see if we need to use mixed mode to route IRQ 0,
instead we always use mixed mode to route IRQ 0 for now. This can be
disabled via the 'NO_MIXED_MODE' kernel option.
- The npx(4) driver now always probes to see if a built-in FPU is present
since this test can now be performed with the new APIC code. However,
an SMP kernel will panic if there is more than one CPU and a built-in
FPU is not found.
- PCI interrupts are now properly routed when using APICs to route
interrupts, so remove the hack to psuedo-route interrupts when the
intpin register was read.
- The apic.h header was moved to apicreg.h and a new apicvar.h header
that declares the APIs used by the new APIC code was added.

Fix copyright comment & FBSDID style nits.

Requested by: bde

- Fix a typo in a comment.
- Use macros for MSR register indexes as well as the bitfields in the
APICBASE MSR.

Use __FBSDID().

Extend CPU_ATHLON_SSE_HACK to cover a few more revisions of Athlon CPUs.

Submitted by: Jon Kuster <kwsn@earthlink.net>
MFC after: 2 weeks

- Move enable_sse()'s prototype to machine/md_var.h.
- Sort definition of cpu_* variables appropriately.
- Move cpu_fxsr out of the magic non-BSS set of variables and stick it in
the BSS along with hw_instruction_sse (make the latter static as well).

Submitted by: bde (partially)

Rename cpuid_cpuinfo to cpu_procinfo. bde requested that I rename this
variable to something in the cpu_* namespace since that's what all the
other cpuid variables were named and cpu_procinfo is what I came up with.

Requested by: bde

Rework part of the previous processor name changes so that we read
cpu_exthigh and cpu_brand in printcpuinfo() instead of in identify_cpu().
We also only do it for known-good values of cpu_vendor which is a bit more
conservative.

Reviewed by: bde (mostly)

- Add a cpu_exthigh variable to hold the highest extended cpuid value
returned from cpuid 0x80000000.
- Add a cpu_brand char array to hold the processor name returned by
cpuid 0x80000002-0x80000004 on AMD, Intel, Transmeta, and possibly
other CPUs.
- Use cpuid to set cpu_exthigh and read the processor name if it is present
in identify_cpu().

Add a cpuid_cpuinfo variable to hold the results of %ebx from cpuid with
%eax of 1 and set it in identify_cpu().

Be consistent about functions being static.

Spotted by: FlexeLint.

Be consistent about "static" functions: if the function is marked
static in its prototype, mark it static at the definition too.

Inspired by: FlexeLint warning #512

Automatically enable CPU_ENABLE_SSE (detect and enable SSE instructions)
if compiling with I686_CPU as a target. CPU_DISABLE_SSE will prevent
this from happening and will guarantee the code is not compiled in.

I am still not happy with this, but gcc is now generating code that uses
these instructions if you set CPUTYPE to p3/p4 or athlon-4/mp/xp or higher.

Fix abuses of cpu_critical_{enter,exit} by converting to
intr_{disable,restore} as well as providing an implemenation of
intr_{disable,restore}.

Reviewed by: jake, rwatson, jhb

Add an option CPU_ATHLON_SSE_HACK which attempts to enable the SSE
feature bit on newer Athlon CPUs if the BIOS has forgotten to enable
it.

This patch was constructed using some info made available by John
Clemens at http://www.deater.net/john/PavilionN5430.html

Reviewed by: -audit
MFC after: 3 weeks

Modify the critical section API as follows:
- The MD functions critical_enter/exit are renamed to start with a cpu_
prefix.
- MI wrapper functions critical_enter/exit maintain a per-thread nesting
count and a per-thread critical section saved state set when entering
a critical section while at nesting level 0 and restored when exiting
to nesting level 0. This moves the saved state out of spin mutexes so
that interlocking spin mutexes works properly.
- Most low-level MD code that used critical_enter/exit now use
cpu_critical_enter/exit. MI code such as device drivers and spin
mutexes use the MI wrappers. Note that since the MI wrappers store
the state in the current thread, they do not have any return values or
arguments.
- mtx_intr_enable() is replaced with a constant CRITICAL_FORK which is
assigned to curthread->td_savecrit during fork_exit().

Tested on: i386, alpha

Mostly cosmetic. Move various variables from .s files to .c files so that
gdb generates debug info for them.

Move cpu_fxsr definition to C code (so debug info is generated) and where
it is easily #ifdef'ed so that we dont miss unintentional references to it.

There is nothing special that requires SSE to be only on 686 class cpus.
This enables 586-only SMP kernels to compile again.

Problem reported by: Jacek Jedrzejczak <jacol@ids.gda.pl>

Unbroke kernel if I686_CPU is not defined.

Forgot this fix from another tree. make enable_sse() a real prototype.

Move init_sse() out of the "GenuineIntel" section, my AthlonMP system
has it, for example, and it works fine.

Activate SSE/SIMD. This is the extra context switching support that
we are required to do if we let user processes use the extra 128 bit
registers etc.

This is the base part of the diff I got from:
http://www.issei.org/issei/FreeBSD/sse.html
I believe this is by: Mr. SUZUKI Issei <issei@issei.org>
SMP support apparently by: Takekazu KATO <kato@chino.it.okayama-u.ac.jp>
Test code by: NAKAMURA Kazushi <kaz@kobe1995.net>, see
http://kobe1995.net/~kaz/FreeBSD/SSE.en.html

I have fixed a couple of style(9) deviations. I have some followup
commits to fix a couple of non-style things.

Switch from save/disable/restore_intr() to critical_enter/exit().

Fix some further english grammar and typo's.

Fix typo's: UPGRADE_CPU_HW_CACHE -> CPU_UPGRADE_HW_CACHE

Major update to the way synchronization is done in the kernel. Highlights
include:

* Mutual exclusion is used instead of spl*(). See mutex(9). (Note: The
alpha port is still in transition and currently uses both.)

* Per-CPU idle processes.

* Interrupts are run in their own separate kernel threads and can be
preempted (i386 only).

Partially contributed by: BSDi (BSD/OS)
Submissions by (at least): cp, dfr, dillon, grog, jake, jhb, sheldonh

Improved Cyrix 486DX supports for NEC PC-98.
- Enable WB cache via CCR2 and CR0.
- Set the need_pre_dma_flush when the CPU_I486_ON_386 option is
defined.

Submitted by: Kaho Toshikazu <kaho@elam.kais.kyoto-u.ac.jp>

Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support
Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is
defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is
enabled through MSR 0x11e. The L2 cache latency value can be
specified by CPU_L2_LATENCY option. Default value of L2 cache latency
is 5.

These options are useful if you use Socket 8 to Socket 370 converter
(e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2
cache of Mendocino Celeron CPUs because they don't know Celeron CPUs.
These options are needles if you use a Coppermine (FCPGA) Celeron or
PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache
is always enabled.

$Id$ -> $FreeBSD$

Kill option FAILSAFE.

PR: i386/12187
Approved by: bde

There are two models of AMD K6-2 Model 8 (c.f. AMD's document), so the
CPU stepping must be checked. Also, fixed print_AMD_info.

Submitted by: Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp>

From the submitter:

CPU_WT_ALLOC does not work correctly for K6-2s of model 8+ and
probably K6-3s (when they appear on the market soon). In addition,
print_AMD_info() incorrectly printfs write allocation's size. I've
fixed them, so they now Do The Right Thing, and added a
"NO_MEMORY_HOLE" option to easily allow 15-16mb range handling for us
K6 and K6-2 users.

Submitted by: Brian Feldman <green@unixhelp.org>

Get rid of uninitialized variable warnings. No bugs found, just
preinitializing some locals to 0 to get rid of the compiler warnings.

- Implement enabling write allocate on AMD K5/K6/K6-2 cpus.
The code was originaly contributed by Kelly Yancey
<kbyanc@freedomnet.com> in PR i386/6269 and revised by Akio Morita
<amorita@meadow.scphys.kyoto-u.ac.jp> and me. Test was performed by
Akio Morita and Toshiomi Moriki <moriki@db.is.kyushu-u.ac.jp>.
- Fix stylistic bug in identcpu.c.
- Update copyright in initcpu.c
- Fix typo in LINT.

PR: 6269 and 6270

Disable local APIC in UP kernel. Intel specification update describes
that local APIC should be disabled in UP system. However, some of old
BIOS does not disable local APIC, and virtual wire mode through local
APIC may cause int 15.

Make FAILSAFE a new-style option.

Fix typo. Option `CPU_SUSP_HLT' didn't work on Cyrix 486DX box.

Submitted by: nyan@wyvern.cc.kogakuin.ac.jp (Takahashi Yoshihiro)

Correct CPU_CYRIX_NO_LOCK fix.
PR: 5121
Pointed out by: Matthew Hunt

Removed unused #includes.

Added two Cyrix 6x86/6x86MX options.

- CPU_CYRIX_NO_LOCK enables weak locking. If this option is not set and
FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared.
- CPU_WT_ALLOC enables write-through allocation.

Treat 6x86MX CPU as 686-class CPU instead of 586-class CPU.

Added CPU_DIRECT_MAPPED_CACHE option which sets L1 cache in direct
mapped mode on Cyrix 486DLC box.

- Use `6x86MX' instead of `M2'. Cyrix officially use `6x86MX' for the
CPU code-named `M2'.

- Use the result of cpuid instruction instead of DIR to identify
6x86MX cpu. DIR0 and DIR1 are not documented in the data sheet, and
cpuid instruction is enabled at reset time.

- Add a function, init_6x86MX() to initialize 6x86MX cpu. It supports
CPU_SUSP_HLT and CPU_IORT options. It always sets NC1 (640K - 1M is
not cached.), and enables L1 cache in write-back mode.

- Fix typo in the comment in identblue().

Add new cpu type, CPU_CY486DX, which shows Cyrix 486S/DX series CPUs,
and initialization routine for those CPUs.

Tested by: Bob Bishop <rb@gid.co.uk>

Don't disable CPU cache in init_486dlc. If BIOS supports Cyrix 486,
BIOS enables CPU cache and other registers. If BIOS does not supports
it, CPU cache is disabled at reset time.

This commit closes PR/3292.

PR: 3292

Fix typo.
Submitted by: Bruce Evans <bde@zeta.org.au>

Oops, I forgot to `cvs add'. This file is a part of new CPU
identification and initialization routines.