- Copy stable/10 (r259064) to releng/10.0 as part of the
10.0-RELEASE cycle.
- Update __FreeBSD_version [1]
- Set branch name to -RC1

[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so
start releng/10.0 at '100' so the branch is started with
a value ending in zero.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

MFC r257856:
Add bits for the AMD features from CPUID function 0x80000001 ECX,
described in the rev. 3.0 of the Kabini BKDG, document 48751.pdf.

Approved by: re (gjb)

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

x86: detect mwait capabilities and extensions, when present

Reviewed by: kib (earlier amd64-only version)
MFC after: 2 weeks

After r205013, amd64 and i386 CPU family and model IDs were printed out
in hexadecimal, but without any 0x prefix, which can be very misleading.

MFC after: 3 days

Recognize the RDRAND instruction feature.

Submitted by: Michael Fuckner michael fuckner net
MFC after: 3 days

Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features.
Note AMD dropped SSE5 extensions in order to avoid ISA overlap with Intel
AVX instructions. The SSE5 bit was recycled as XOP extended instruction
bit, CVT16 was deprecated in favor of F16C (half-precision float conversion
instructions for AVX), and the remaining FMA4 (4-operand FMA instructions)
gained a separate CPUID bit. Replace non-existent references with today's
CPUID specifications.

Define "Hypervisor Present" bit. This bit is used by several hypervisors to
identify CPUs running under emulation. Currently QEMU-KVM, Xen-HVM, VMware,
and MS Hyper-V are known to set this bit.

MFC after: 3 days

Probe capability to find effective frequency. When the TSC is P-state
invariant, APERF/MPERF ratio can be used to find effective frequency.

Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta
CPUs. These CPUs need explicit MSR configuration to expose ceratin CPU
capabilities (e.g., CMPXCHG8B) to work around compatibility issues with
ancient software. Unfortunately, Rise mP6 does not set the CX8 bit in CPUID
and there is no MSR to expose the feature although all mP6 processors are
capable of CMPXCHG8B according to datasheets I found from the Net. Clean up
and simplify VIA PadLock detection while I am in the neighborhood.

Detect NSC/AMD Geode SC1100 properly, not just Stepping 0. Although it is
unclear that "TSC stops ticking with HLT instruction" problem is present
with other steppings, it is limited to Stepping 0 for now.

Deprecate rarely used tsc_is_broken. Instead, we zero out tsc_freq because
it is almost always used with tsc_freq any way.

Remove stale comments about P-state invariant TSC and fix style(9) nits.

Do not register a event handler for CPU freqency changes when it is found
P-state invariant. This is continuation of r216274.

Probe P-state invariant TSC from rightful place.

Use intr_disable() and intr_restore() instead of frobbing the flags register
directly to disable interrupts.

Reviewed by: bde (earlier version)
MFC after: 2 weeks

Display PCID capability of CPU and add CPUID define for it.

MFC after: 1 week

Remove unused i586 optimized bcopy/bzero/etc implementations that utilize
FPU registers for copying. Remove the switch table and jumps from
bcopy/bzero/... to the actual implementation.
As a side-effect, i486-optimized bzero is removed.

Reviewed by: bde
Tested by: pho (previous version)

Add definitions for Intel AESNI CPUID bits and print the capabilities
on boot.

Hardware provided by: Sentex Communications
MFC after: 1 week

Print out the family and model from the cpu_id. This is especially useful
given the advent of the extended family and extended model fields. The
values are printed in hex to match their common usage in documentation.

Submitted by: Alexander Best
MFC after: 1 week

x86 cpu features: add MOVBE reporting and flag

The check is glimpsed from Linux and OpenSolaris.
MOVBE instruction is found in Intel Atom processors.

Fix cpu model for PODP5V83. It is P24T, not P54T.
Also remove redundant 'Overdrive' word.

Pointed out by: SATOU Tomokazu (tomo1770 at maple ocn ne jp)
MFC after: 1 week

Strip from messages for users external URLs the project cannot directly
control.

Requested by: kib, rwatson

Opteron rev E family of processor expose a bug where, in very rare
ocassions, memory barriers semantic is not honoured by the hardware
itself. As a result, some random breakage can happen in uninvestigable
ways (for further explanation see at the content of the commit itself).

As long as just a specific familly is bugged of an entire architecture
is broken, a complete fix-up is impratical without harming to some
extents the other correct cases.
Considering that (and considering the frequency of the bug exposure)
just print out a warning message if the affected machine is identified.

Pointed out by: Samy Al Bahra <sbahra at repnop dot org>
Help on wordings by: jeff
MFC: 3 days

Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce
unnecessary #ifdef's for shared code between them.

Unlock the largest standard CPUID on Intel CPUs for both amd64 and i386 and
fix SMP topology detection. On i386, we extend it to cover Core, Core 2,
and Core i7 processors, not just Pentium 4 family, and move it to better
place. On amd64, all supported Intel CPUs should have this MSR.

- Add support for cpuid leaf 0xb. This allows us to determine the
topology of nehalem/corei7 based systems.
- Remove the cpu_cores/cpu_logical detection from identcpu.
- Describe the layout of the system in cpu_mp_announce().

Sponsored by: Nokia

VIA Nano processor has a special MSR (CENT_HARDWARECTRL3) bit 32 to determine
whether TSC is P-state invariant or not. In fact, this MSR is writable but
we just leave it at the BIOS default for now.

Add basic i386 support for VIA Nano processors.

Add more CPUID bits from AMD CPUID Specification Rev. 2.28.

According to "Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3B: System Programming Guide, Part 2", CPUs with family 0x6 and model
above or 0xE and CPUs with family 0xF and model above or 0x3 have invariant
TSC.

Use newly introduced cpu_vendor_id to make invariant TSC detection more
clearer and merge r185295 to amd64.

Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").

Reviewed by: jhb, peter (early amd64 version)

Core i7 supports invaliant TSC and the presense is presented on
this CPUID information, according to recently updated AP485.

Really fix i386 test this time.
A whole stack of pointyhat to me, please.

Add AMD Family 0Fh, Model 6Bh, Stepping 2 to the list of invariant TSCs
and fix i386 test.

Fix compiler error with missing/unneded ')'

Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher
even if BIOS does not advertise it.

Turn off CPU frequency change notifiers when the TSC is P-state invariant
or it is forced by setting 'kern.timecounter.invariant_tsc' tunable
to non-zero.

Detect Advanced Power Management Information for AMD CPUs.

- Recognize SAVE and OSXSAVE extended processor features.

Approved by: kib (mentor)
MFC after: 1 month

MFamd64: More CPUID feature flags: SSE4, X2APIC, POPCNT, DTES64, and 1GB
large pages.

MFC after: 1 month

The VM system no longer uses setPQL2(). Remove it and its helpers.

- Remove the old smp cpu topology specification with a new, more flexible
tree structure that encodes the level of cache sharing and other
properties.
- Provide several convenience functions for creating one and two level
cpu trees as well as a default flat topology. The system now always
has some topology.
- On i386 and amd64 create a seperate level in the hierarchy for HTT
and multi-core cpus. This will allow the scheduler to intelligently
load balance non-uniform cores. Presently we don't detect what level
of the cache hierarchy is shared at each level in the topology.
- Add a mechanism for testing common topologies that have more information
than the MD code is able to provide via the kern.smp.topology tunable.
This should be considered a debugging tool only and not a stable api.

Sponsored by: Nokia

With the recent change to enable CPU brands from the VIA chips, the
code to add padlock features to the CPU model on VIA CPUs was no longer
effective. Change the code to instead output a separate printf during
dmesg for VIA Padlock features similar to other cpuid feature bitmasks.

MFC after: 1 week

- Check for the extended CPUID registers on VIA CPUs so we can get the
brand string.
- Fix a nit in the previous commit. "Eden" is a product name, not a core
name. The new ID is still for an "Esther" core.

Support the VIA C7 Eden CPU and treat it just like a C7 Esther. We may
want to adjust this code to just assume that all CPUs >= Esther should
be checked for the extended cpuid flags register.

MFC after: 3 days
PR: i386/119491

Add descriptive comment to PDCM entry.

Remove a pointless bootverbose message.

MFC after: 3 days

Add feature name for features2 bit 15.

PR: i386/113133
Submitted by: Pankov Pavel <pankov_p@mail.ru>
MFC after: 3 days

On AMD's Geode LX: Force the TSC to run through core-suspension so we can
use it as a timecounter.

Sponsored by: Soekris Engineering

Add the PG_NX support for i386/PAE.

Reviewed by: alc

Add an interface for drivers to be notified of changes to CPU frequency.
cpufreq_pre_change is called before the change, giving each driver a chance
to revoke the change. cpufreq_post_change provides the results of the
change (success or failure). cpufreq_levels_changed gives the unit number
of the cpufreq device whose number of available levels has changed. Hook
in all the drivers I could find that needed it.

* TSC: update TSC frequency value. When the available levels change, take the
highest possible level and notify the timecounter set_cputicker() of that
freq. This gets rid of the "calcru: runtime went backwards" messages.
* identcpu: updates the sysctl hw.clockrate value
* Profiling: if profiling is active when the clock changes, let the user
know the results may be inaccurate.

Reviewed by: bde, phk
MFC after: 1 month

- Add macros for newly added CPUID bits in the corresponding header files.
- Use correct capticalization in xTPR as Intel uses in their documents.
- Use proper description instead of vendor code name in comment.

display two new Intel feature bits

Submitted by: "Rui Paulo" <rpaulo@gmail.com>
MFC after: 2 weeks

Add another CPUID for AMD CPUs and fix style(9) while I am here.

Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors.

Remove old XXX comment about possibly adding a print_Intel_info() function
to dump CPUID level=2 stuff. A print_INTEL_info() function that does just
that was added a while ago.

Dont overwrite cpu_model in the case of Via's C3-CPU.

Noticed by: Mike Tancsa
MFC after: 2 days

Correct spelling of 3DNow!.

fix typo in identcpu.c and add one define to specialreg.h.

MFC after: 1 week

forgot to add MFC, since its used on -stable and compile-tested on -current.

MFC after: 1 week

First step to identify and initialize the newer VIA C7 CPU
as found in a VIA EPIA EN-15000 board.

Obtained from: large parts from OpenBSD

Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register.

Clear bit 22 in MSR IA32_MISC_ENABLE, according to Intel document,
when the bit 22 is set to 1, CPUID with EAX=0 returns a maximum
value in EAX[7..0] of 3, when set to 0(default), CPUID with EAX=0
returns the number corresponding to the maximum standard function
supported. On my machine, BIOS sets the bit to 1 to make it to be
compatible with old OS, this causes dual-core Pentium-D (two
physical cores) to be identified as hyperthreading (two logical
cores) by function mp_topology().

Add another Intel CPU feature flag, xTPR (Send Task Priority Messages).

Check if deterministic cache parameters leaf is valid before use.

- use a more common style to print memory sizes
- add some more cache sizes (2nd and 3rd level) [1]

Submitted by: HATANOU Tomomi <hatanou@infolab.ne.jp> [1]
PR: 91328 [1]

It seems bit 5 of cpu_feature2 is the VMX (Virtual Machine Extensions)
bit. While I'm here, delete a comment that was cut and past from the
cpu_features code that doesn't belong here.

Avoid calling CPUID function 0x02 if the CPU reports no support for
it. The former code used to hang older Intel CPUs by trying to get
non-existent TLB info 2^32 times.

Reduce code duplication around the calls to CPUID 0x02 by using
do-while loops.

PR: i386/92977
Tested by: cy

Under verbose mode, correctly report L2 cache information
for CPU which supports CPUID function 8000_0006h.

Tested on: Pentum-M 750

Fix bug in L2 cache size detection code for CPU which supports CPUID
function 8000_0006h.

Tested on: Pentum-M 750

Correctly report L2 cache size according to its code comment.
Tested on my Dual PIII machine.

We don't support I386_CPU in 6.0 and later. This file can be cleaned
up some to assume that '#if defined(I486_CPU) || defined(I586_CPU) ||
defined(I686_CPU)' is true.

Suggested by: jhb
Reviewed by: jhb

- Make sure the cpu_exthigh variable is initialized (page coloring case). [1]
- Remove a conditional in the AMD cache detection, it's always false. [2]
- Don't try to detect a cache if only compiled for i386.

Analyzed by: Antoine Brodin <antoine.brodin@laposte.net> [1]
Submitted by: Antoine Brodin <antoine.brodin@laposte.net> [2]

MI changes:
- provide an interface (macros) to the page coloring part of the VM system,
this allows to try different coloring algorithms without the need to
touch every file [1]
- make the page queue tuning values readable: sysctl vm.stats.pagequeue
- autotuning of the page coloring values based upon the cache size instead
of options in the kernel config (disabling of the page coloring as a
kernel option is still possible)

MD changes:
- detection of the cache size: only IA32 and AMD64 (untested) contains
cache size detection code, every other arch just comes with a dummy
function (this results in the use of default values like it was the
case without the autotuning of the page coloring)
- print some more info on Intel CPU's (like we do on AMD and Transmeta
CPU's)

Note to AMD owners (IA32 and AMD64): please run "sysctl vm.stats.pagequeue"
and report if the cache* values are zero (= bug in the cache detection code)
or not.

Based upon work by: Chad David <davidc@acns.ab.ca> [1]
Reviewed by: alc, arch (in 2004)
Discussed with: alc, Chad David, arch (in 2004)

Prepare for MACHINE and hw.machine switching to "pc98" on FreeBSD/pc98.

Reviewed by: nyan

Fix spelling mistake.

Submitted by: kris

Redo physical/logical CPU count.

Suggested by: jhb

Split displaying number of physical and logical cores.

For AMD processors, nullify CPUID.HTT. FreeBSD has no need for the
information it conveys, and it is only confusing people.
This fixes incorrect output in the previous commit.

- Print number of physical/logical cores and more CPUID info.
- Add newer CPUID definitions for future use.

Many thanks to Mike Tancsa <mike at sentex dot net> for providing test
cases for Intel Pentium D and AMD Athlon 64 X2.

Approved by: anholt (mentor)

Begin promoting the AMD-originated feature flags to first class flags, now
that newer Intel cpu hardware implements them too. This includes things
like the NX (pte no-execute) flag for execute protection. We'll need to
reference this for implementing no-exec in pmap.c at some point.

Some feature flags are duplicated in both the Intel-orignated bits and
the AMD bits. Suppress the the duplicates correctly - the old code
assumed they were a 1:1 mapping which is not correct. We can't just mask
off the bits present in cpu_feature.

Converge with amd64 where this originated from.

Intel cpu's that implement any AMD features will report them in dmesg now.

Approved by: re

Chop a '>' in a feature name (RSVD2>) that snuck in;
this now balances the <> flags displayed at boot, e.g. without this
Features2=0x41d<SSE3,RSVD2>,MON,DS_CPL,CNTX-ID>

MFC after: 1 week

Add the 2nd word of IA32 feature flags. This includes things such as SSE3.

Obtained from: sys/amd64/amd64/identcpu.

netchild's mega-patch to isolate compiler dependencies into a central
place.

This moves the dependency on GCC's and other compiler's features into
the central sys/cdefs.h file, while the individual source files can
then refer to #ifdef __COMPILER_FEATURE_FOO where they by now used to
refer to #if __GNUC__ > 3.1415 && __BARC__ <= 42.

By now, GCC and ICC (the Intel compiler) have been actively tested on
IA32 platforms by netchild. Extension to other compilers is supposed
to be possible, of course.

Submitted by: netchild
Reviewed by: various developers on arch@, some time ago

Move the author's copyright notice to match the initial LongRun import
now that we have split out this support into longrun.c

Initiate deorbit burn sequence for 80386 support in FreeBSD: Remove
80386 (I386_CPU) support from the kernel.

The NatSemi (now AMD) Geode SC1100 needs special treatment here and there
because it is an embedded gadget. Give it it's own value for the "cpu"
variable and add code to reset it lacking a keyboard controller.

struct cpu_nameclass is a private to identcpu.c, move it there.

I hate noticing bugs after committing. :-(
ALWAYS set up the CPU base identity string. THEN optionally
add features.

Add extra output to show when VIA C3 Nehemiah CPUs have hardware
Random Number Generator (RNG) and/or Advanced Cryptography Engine
(ACE).

Print cpu features for crusoe processors.

These are changes to allow to use the Intel C/C++ compiler (lang/icc)
to build the kernel. It doesn't affect the operation if gcc.

Most of the changes are just adding __INTEL_COMPILER to #ifdef's, as
icc v8 may define __GNUC__ some parts may look strange but are
necessary.

Additional changes:
- in_cksum.[ch]:
* use a generic C version instead of the assembly version in the !gcc
case (ASM code breaks with the optimizations icc does)
-> no bad checksums with an icc compiled kernel
Help from: andre, grehan, das
Stolen from: alpha version via ppc version
The entire checksum code should IMHO be replaced with the DragonFly
version (because it isn't guaranteed future revisions of gcc will
include similar optimizations) as in:
---snip---
Revision Changes Path
1.12 +1 -0 src/sys/conf/files.i386
1.4 +142 -558 src/sys/i386/i386/in_cksum.c
1.5 +33 -69 src/sys/i386/include/in_cksum.h
1.5 +2 -0 src/sys/netinet/igmp.c
1.6 +0 -1 src/sys/netinet/in.h
1.6 +2 -0 src/sys/netinet/ip_icmp.c

1.4 +3 -4 src/contrib/ipfilter/ip_compat.h
1.3 +1 -2 src/sbin/natd/icmp.c
1.4 +0 -1 src/sbin/natd/natd.c
1.48 +1 -0 src/sys/conf/files
1.2 +0 -1 src/sys/conf/files.amd64
1.13 +0 -1 src/sys/conf/files.i386
1.5 +0 -1 src/sys/conf/files.pc98
1.7 +1 -1 src/sys/contrib/ipfilter/netinet/fil.c
1.10 +2 -3 src/sys/contrib/ipfilter/netinet/ip_compat.h
1.10 +1 -1 src/sys/contrib/ipfilter/netinet/ip_fil.c
1.7 +1 -1 src/sys/dev/netif/txp/if_txp.c
1.7 +1 -1 src/sys/net/ip_mroute/ip_mroute.c
1.7 +1 -2 src/sys/net/ipfw/ip_fw2.c
1.6 +1 -2 src/sys/netinet/igmp.c
1.4 +158 -116 src/sys/netinet/in_cksum.c
1.6 +1 -1 src/sys/netinet/ip_gre.c
1.7 +1 -2 src/sys/netinet/ip_icmp.c
1.10 +1 -1 src/sys/netinet/ip_input.c
1.10 +1 -2 src/sys/netinet/ip_output.c
1.13 +1 -2 src/sys/netinet/tcp_input.c
1.9 +1 -2 src/sys/netinet/tcp_output.c
1.10 +1 -1 src/sys/netinet/tcp_subr.c
1.10 +1 -1 src/sys/netinet/tcp_syncache.c
1.9 +1 -2 src/sys/netinet/udp_usrreq.c

1.5 +1 -2 src/sys/netinet6/ipsec.c
1.5 +1 -2 src/sys/netproto/ipsec/ipsec.c
1.5 +1 -1 src/sys/netproto/ipsec/ipsec_input.c
1.4 +1 -2 src/sys/netproto/ipsec/ipsec_output.c

and finally remove
sys/i386/i386 in_cksum.c
sys/i386/include in_cksum.h
---snip---
- endian.h:
* DTRT in C++ mode
- quad.h:
* we don't use gcc v1 anymore, remove support for it
Suggested by: bde (long ago)
- assym.h:
* avoid zero-length arrays (remove dependency on a gcc specific
feature)
This change changes the contents of the object file, but as it's
only used to generate some values for a header, and the generator
knows how to handle this, there's no impact in the gcc case.
Explained by: bde
Submitted by: Marius Strobl <marius@alchemy.franken.de>
- aicasm.c:
* minor change to teach it about the way icc spells "-nostdinc"
Not approved by: gibbs (no reply to my mail)
- bump __FreeBSD_version (lang/icc needs to know about the changes)

Incarnations of this patch survive gcc compiles since a loooong time,
I use it on my desktop. An icc compiled kernel works since Nov. 2003
(exceptions: snd_* if used as modules), it survives a build of the
entire ports collection with icc.

Parts of this commit contains suggestions or submissions from
Marius Strobl <marius@alchemy.franken.de>.

Reviewed by: -arch
Submitted by: netchild

Move LongRun support out of identcpu.c, where it hardly belongs, into its
own file and make it opt-in, not mandatory, depending on CPU_ENABLE_LONGRUN
config(8) option.

Discussed with: nate
MFC after: 2 weeks

Update includes for new interrupt code.

Add AMD Features NX and LM.

Add constants for entries in the IDT and use those instead of magic
numbers.

Fix copyright comment & FBSDID style nits.

Requested by: bde

Improve the C3 CPU identification. I didn't notice that the CPU id
was masked. However KIMURA Yasuhiro-san noticed my mistake and was
kind enough to provide a better patch in PR 55581. I've merged that
into the routine. Hopefully I've not overlooked anything this time.

MFC After: 5 days

Add many new VIA C3 CPU types now that they appear to be available in
machines (at least in Japan).

Submitted by: Masahiko KIMOTO-san
PR: 55578

Update to recognize Geode and note that the TSC seems broken.

Fixed style bugs in rev.1.94 before MFCing it (for large C asm statements,
use "\n\" instead of "\" at the end of each source line, and don't use
semicolons). Fixed some older style bugs on the same lines (mainly
English errors in comments).

Use __FBSDID().

Add missing break;

Found by: FlexeLint

Warns fixing. Protect against inappropriate linting, and mark
GCC-specific assemble code as such (in #ifdefs). Fix an easy
static variable warning while I'm here.

Add a sysctl that records and reports the CPU clock rate calculated
at boot. Funny how often this trivial piece of information crops up
in embedded boxen.

Sponsored by: St. Bernard Software

Define ovbcopy() as a macro which expands to the equivalent bcopy() call,
to take care of the KAME IPv6 code which needs ovbcopy() because NetBSD's
bcopy() doesn't handle overlap like ours.

Remove all implementations of ovbcopy().

Previously, bzero was a function pointer on i386, to save a jmp to
bzero_vector. Get rid of this microoptimization as it only confuses
things, adds machine-dependent code to an MD header, and doesn't really
save all that much.

This commit does not add my pagezero() / pagecopy() code.

Including <sys/stdint.h> is (almost?) universally only to be able to use
%j in printfs, so put a newsted include in <sys/systm.h> where the printf
prototype lives and save everybody else the trouble.

Expand some #ifdef's to fix I386_CPU compile.

Reported by: Andy Farkas <andyf@speednet.com.au>

Make tsc_freq a 64bit quantity.

Inspired by: http://www.theinquirer.net/?article=7481

Rename cpuid_cpuinfo to cpu_procinfo. bde requested that I rename this
variable to something in the cpu_* namespace since that's what all the
other cpuid variables were named and cpu_procinfo is what I came up with.

Requested by: bde

Remove earlysetcpuclass() as it has been OBE.

Suggested by: bde

Rework part of the previous processor name changes so that we read
cpu_exthigh and cpu_brand in printcpuinfo() instead of in identify_cpu().
We also only do it for known-good values of cpu_vendor which is a bit more
conservative.

Reviewed by: bde (mostly)

Consistently use spaces in between arguments to strcmp(). Whitespace
only.

- Use cpu_exthigh instead of executing cpuid again to retrieve it for the
print_AMD_foo() functions.
- Add a brand name table for the brand index provided on Intel CPU's in
%ebx after cpuid 1.
- For Intel CPUs, if we don't get a processor name from the extended cpuid
then use the brand index in cpuid_cpuinfo to pick a name from the brand
table and copy that name into cpu_brand.
- Replace the duplicated code to use the extended cpuid to replace
cpu_model with the processor name in the AMD and Transmeta sections of
printcpuinfo() with generic code that replaces cpu_model with
cpu_brand if cpu_brand is not an empty string. We also trim leading
spaces from cpu_brand prior to doing this since at least some processor
names (notably those of Intel CPUs) have leading spaces in the name.
- Give print_AMD_features() its own private regs[] array since
printcpuinfo() doesn't use the one it has anymore.

Bah, get the test for more than one logical CPU right so we don't bogusly
claim a CPU has HT support when it lists 0 or 1 logical CPU's per physical
processor.

If the boot processor supports hyperthreading and contains more than one
logical CPU, display the number of logical CPUs per physical processor
underneath the list of CPU features.

Document bit 31 of the cpuid features word as PBE (Pending Break Enable).

Change the support for AMDs ElanSC520 CPU from being a device driver to
be
options CPU_ELAN
(NB: Soekris.com users!)

It is cleaner this way. We still recognize the cpu on the host-pci bridge.

Document why the has_f00f_bug variable is initialised rather than placed into
the BSS (so that it can be binary-patched).

Inspired by: bde

The Elan SC520 MMCR is actually 16bit wide, so u_char is inconvenient.

Add initialization code for the AMD Elan sc520 which maps the MMCR
into KVM and sets the i8254 frequency to the correct value.

For what it's worth, fix the compilation of an I386_CPU-only kernel
now that certain warnings are fatal.

Add generalized power profile code.
This makes other power-management system (APM for now) to be able to
generate power profile change events (ie. AC-line status changes), and
other kernel components, not only the ACPI components, can be notified
the events.

- move subroutines in acpi_powerprofile.c (removed) to kern/subr_power.c
- call power_profile_set_state() also from APM driver when AC-line
status changes
- add call-back function for Crusoe LongRun controlling on power
profile changes for a example

Fix typos in some comments.

PR: i386/35114
Submitted by: Gavin Atkinson <gavin.atkinson@ury.york.ac.uk>

Move do_cpuid() from a identcpu.c into cpufunc.h.

Cosmetic changes:
- Collected i486 identification codes in one place like
586 and 686.
- Merged two cases (0x470 and 0x490) for `Enhanced Am486DX4
Write-Back.'
- Replaced `unknown' into `Unknown'.

Submitted by: chi@bd.mbn.or.jp (Chiharu Shibata)

Recognize VIA C3 Samuel 2.

MFC after: 3 days

List bit 18 (reserved, apparently present on thunderbird cpus)
and bit 19 (athlon XP/MP rev 0x662 and later) for amd_features.

Submitted by: dwcjr

Change <b28> to HTT (Hyperthreading technology). If this flag is set then
cpuid with %eax=1 will return a logical cpu count in bits 16-23 of %ebx.
Bit 29 is actually 'TM' according to AP-485. This signifies the presence
of the thermal control circuit (which I believe can slow the clock down
to reduce core temperature).

cpuid bit 30 is 'IA64', for when you're running in i386 mode on an ia64
cpu. (This is for either userland apps running in i386 mode on an ia64
OS, or when the cpu is in i386 legacy mode running an i386 OS).

Correct the input/output/clobber specifications for the cpuid
instruction. Stefan Keller <dres@earth.serd.org> noticed that CPU
identification was broken when compiled with -O2, and tracked it
down to the asm statement, which was storing values into memory
without specifying that memory was modified. He submitted a patch
which added "memory" as a clobber, but I refined it further to
arrive at this version.

MFC after: 3 days

gcc-3 has objections about the bluetrap6 and bluetrap13 inline asm
functions. Apparently multi-line string asm arguments are deprecated.

Add Transmeta Crusoe LongRun support.

Submitted by: Tamotsu HATTORI <athlete@kta.att.ne.jp>
Reviewed by: arch@ folks
MFC after: 1 week

Recognize FC-PGA2 Pentium III (Tualatin).

Add code to detect Transmeta Crusoe cpus.

Stop doing runtime checking on i386 cpus for cpu class. The cpu is
slow enough as it is, without having to constantly check that it really
is an i386 still. It was possible to compile out the conditionals for
faster cpus by leaving out 'I386_CPU', but it was not possible to
unconditionally compile for the i386. You got the runtime checking whether
you wanted it or not. This makes I386_CPU mutually exclusive with the
other cpu types, and tidies things up a little in the process.

Reviewed by: alfred, markm, phk, benno, jlemon, jhb, jake, grog, msmith,
jasone, dcs, des (and a bunch more people who encouraged it)

Assembler fixes.

Fix opcodes that were typed as ".byte 0xNN, 0xMM" when an older
assembler could not recognise the newer Pentium instructions.
Reviewed by: jhb

Remove unneeded #include <sys/proc.h> lines.

Fill in some more missing bits from cpu_features according to the Intel
Pentium4 cpuid docs.

First shot at identifying the Pentum 4 acording to our reading of the
the cpu_id extensions in the Intel docs. There is more info available.
See the following URL for more details.
http://developer.intel.com/design/processor/future/manuals/CPUID_Supplement.htm

Requested by: Intel

Fix spelling of Katmai [Katami].

Recognize new Pentium III Xeon (stepping A0).

PR: 21233
Submitted by: ade

Major update to the way synchronization is done in the kernel. Highlights
include:

* Mutual exclusion is used instead of spl*(). See mutex(9). (Note: The
alpha port is still in transition and currently uses both.)

* Per-CPU idle processes.

* Interrupts are run in their own separate kernel threads and can be
preempted (i386 only).

Partially contributed by: BSDi (BSD/OS)
Submissions by (at least): cp, dfr, dillon, grog, jake, jhb, sheldonh

Recognize Coppermine Celeron processors whose CPU ID = 0x68?. They
were recognized as "Pentium III/Pentium III Xeon."

I mentioned yesterday that I could use some work, and Kelly says, "Commit my
PRs!" So here I go.

Add definitions for some of the AMD CPU feature bits. Also add a comment on
where to find the rest of them. This is a purely cosmetic change.

PR: i386/14438
Submitted by: Kelly Yancey <kbyanc@egroups.net>

Simplify messages of Pentium II, Pentium II Xeon, Celeron, Pentium III
and Pentium III Xeon CPUs. If a CPU is one of Pentium II, Pentium II
Xeon and Celeron, the message is always "Pentium II/Pentium II
Xeon/Celeron". If a CPU is one of Pentium III and Pentium III Xeon,
the message is always "Pentium III/Pentium III Xeon".

A processor with the CPUID of 0x?8? is Pentium III.
(aka Coppermine)

Noticed by: Satoshi Sawada <k-sawata@gnoc2.comminet.or.jp>
Reviewd by: Takuma Yamada <fuzzy2@st.rim.or.jp>

Add text for the Athlon's MMX and 3DNow! (DSP) instruction extensions
to print_AMD_features.

Recognize Pentium II w/ CPUID = 0x6XX and Pentium III Xeon w/ CPUID =
0x7XX.

Pointed out by: Brian Somers <brian@Awfulhak.org>

Display CPU (BSP) clock speed on SMP systems.

System clock don't update, because C6's TSC stop count up when run
HALT instruction.

PR: 13683
Submitted by: IMAI Takeshi <take-i@ceres.dti.ne.jp>
Reviewed by: phk

Add text for the PN (Processor serial number) and XMM (extended SIMD/MMX2/
support), as well as a bunch of comments for what the various bits mean
(those that I remember anyway).

$Id$ -> $FreeBSD$

There may exist two kinds of IBM BlueLightning CPU. One is that 5/2
test does not change undefined flag like Cyrix CPUs. Another is that
5/2 test changes undefined flag like Intel CPUs. Latter one could not
be detected and was recognized 486DX CPU. To solve this,
finishidentcpu() calls identblue() when cpu_vendor is null string
(that is, CPUID instruction is not supported) and cpu == CPU_486.
Tests have been done on IBM BlueLightning CPUs, i486SX and i486DX.

Quieten gcc paranoia.

Typo: s/0ff0/0xff0/

Add Centaur/IDT WinChip support.

Why in the world do people put breaks at the end of a switch's default case?

I made some cleanups, rearranged things a bit, and made AMD Features default
printing on CPUs that have it.
If there are no objections, I'll MFC all recent changes (harmless, really)
to 3.2 and PAO.

Add an extra space to " AMD Features=" to make it line up well.

K6-III CPUs are now case:d in the appropriate switch; also, in
print_AMD_info(), L2 internal cache is shown, as are AMD's special CPUID
infos:

CPU: AMD-K6(tm) 3D processor (350.81-MHz 586-class CPU)
Origin = "AuthenticAMD" Id = 0x58c Stepping=12
Features=0x8021bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,PGE,MMX>
AMD Features=0x808029bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,SYSCALL,PGE,MMX,3DNow!>

PR: kern/12512
Submitted by: Louis A. Mamakos <louie@TransSys.COM>

Only include AMD wt_alloc routines if I586_CPU is defined. Fixes
CPU_WT_ALLOC for cyrix chips.

Submitted by: "Brian Smith" <dbsoft@technologist.com>

This commit gives support for the Rise mP6 CPU. It has two changes:
1. Rise is recognized in identdcpu.c.
2. The TSC is not written to. A workaround for the CPU bug is being
applied to clock.c (the bug being that the mP6 has TSC enabled
in its CPUID-capabilities, but it only supports reading it. If we
try to write to it (MSR 16), a GPF occurs.) The new behavior is that
FreeBSD will _not_ zero the TSC. Instead, we do a bit of 64-bit
arithmetic.

Reviewed by: msmith
Obtained from: unfurl & msmith

Stop the TSC from being used as timecounter on K5/step0 machines.

[Forgot to commit this in the batch a few days ago.]

Fixed profiling of elf kernels. Made high resolution profiling compile
for elf kernels (it is broken for all kernels due to lack of egcs support).

Renaming of many assembler labels is avoided by declaring by declaring
the labels that need to be visible to gprof as having type "function"
and depending on the elf version of gprof being zealous about discarding
the others. A few type declarations are still missing, mainly for SMP.

PR: 9413
Submitted by: Assar Westerlund <assar@sics.se> (initial parts)

Add sysctl descriptions to many SYSCTL_XXXs

PR: kern/11197
Submitted by: Adrian Chadd <adrian@FreeBSD.org>
Reviewed by: billf(spelling/style/minor nits)
Looked at by: bde(style)

Fix two tests against hex. values for CPUID.

PR: i386/10050
Submitted by: Kevin Day <toasty@dragondata.com>

Bit 24 of the Feature Flag is FXSR (for Fast FP Save and Restore).

Reminded by: Francis Dupont <Francis.Dupont@inria.fr>

Recognize Pentium II Xeon, Celeron and Pentium III cpus. Because CPU
names are printed on their packages and shown by BIOS, kernel does not
need to show details.

PR: 8751, 9320 and 9463

There are two models of AMD K6-2 Model 8 (c.f. AMD's document), so the
CPU stepping must be checked. Also, fixed print_AMD_info.

Submitted by: Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp>

Don't put operands in clobber lists, since this is dubious for old
versions of gcc and broken for current versions of egcs.

Cleaned up the asm statement for do_cpuid() a little.

Submitted by: "John S. Dyson" <dyson@iquest.net> but rewritten by me

Moved declarations related to copying and zeroing to the right place.

From the submitter:

CPU_WT_ALLOC does not work correctly for K6-2s of model 8+ and
probably K6-3s (when they appear on the market soon). In addition,
print_AMD_info() incorrectly printfs write allocation's size. I've
fixed them, so they now Do The Right Thing, and added a
"NO_MEMORY_HOLE" option to easily allow 15-16mb range handling for us
K6 and K6-2 users.

Submitted by: Brian Feldman <green@unixhelp.org>

Print out information for write-allocate of AMD CPUs.

Submitted by: Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp>

- Implement enabling write allocate on AMD K5/K6/K6-2 cpus.
The code was originaly contributed by Kelly Yancey
<kbyanc@freedomnet.com> in PR i386/6269 and revised by Akio Morita
<amorita@meadow.scphys.kyoto-u.ac.jp> and me. Test was performed by
Akio Morita and Toshiomi Moriki <moriki@db.is.kyushu-u.ac.jp>.
- Fix stylistic bug in identcpu.c.
- Update copyright in initcpu.c
- Fix typo in LINT.

PR: 6269 and 6270

Fixed printf format errors.

Don't pretend to support ix86's with 16-bit ints by using longs just to
ensure 32-bit variables. Doing so mainly bogotified some printf formats.

Fixed disorder in md_var.h.

Add PSE36 to the bits we know by name.

Use switch instead of if/else chain for 686 model identification.
Add precise model identification for 586-family CPUs.

Correctly identify the precise CPU model within the 686 family: instead
of just printing "Pentium Pro", check the model (cpu_id & 0xf0) and print
the appropriate information.

Missing parens caused cpu features not to be printed for cyrix >= M2/MX.
Althought the comments say the datasheet doesn't list the device ID
registers on the M2/MX, they seem to be there and quite alive.
(It's interesting to note that the M2/MX calls itself a 686 class cpu but
is missing a heck of a lot of features, including VME, PGE, PSE, etc)

Add the PAT cpuid feature.

Support compiling with `gcc -ansi'.

Use RDMSR instruction instead of WRMSR.

Execute cpuid if BIOS disables cpuid instruction of Cyrix 6x86MX CPU.

Undo previous commit. The cpuid symbol has been already used by SMP
stuff.

Pointed-out by: Manfred Antar <root@mantar.slip.netcom.com>

Execute cpuid if BIOS disables cpuid instruction of Cyrix 6x86MX CPU,
and store its result into cpu_id and cpu_feature variables.

Tested by: Simon Coggins <chaos@ultra.net.au>

Even though BIOS writer's guide recommends cpuid instruction of Cyrix
6x86MX CPU is enabled (BIOS should not disable it), some BIOS disables
it via CCR4. In this case, cpu variable becomes CPU_486 and
identblue() is called. Because Cyrix 6x86MX has MSR and doesn't have
MSR1002, wrmsr instruction generates general protection fault.

Tested by: Simon Coggins <chaos@ultra.net.au>

AMD calls the PR166 and PR200, models 2 and 3 respectively.

Update AMD URL for CPU recognition docs.

Rename "i586_ctr" to "tsc" (both upper and lower case instances).
Fix a couple of printfs too.

Warning: This changes the names of a couple of kernel options!

After consultation with David, change
#ifndef NO_F00F_HACK
to
#if defined(I586_CPU) && !defined(NO_F00F_HACK)

Work around for the Intel Pentium F00F bug; this is Intel's recommended
workaround. Note that this currently eats up two pages extra in the system;
this could be alleviated by aligning idt correctly, and then only dealing with
that (as opposed to the current method of allocated two pages and copying the
IDT table to that, and then setting that to be the IDT table).

Remove a bunch of variables which were unused both in GENERIC and LINT.

Found by: -Wunused

Identify MediaGX CPU correctly. Old MeidaGX CPU and GXm CPU are
distinguished. CPU-classes of MeidaGX CPU and GXm CPU are 486-class
and 586-class, respectively.

PR: 4936

Fix rare 6x86 CPU whose DIR0 = 0x20 - 0x28 case.

Don't include <machine/cputypes.h> or declare cputype/class interfaces
in <machine/cpu.h>. Moved the declarations to <machine/cputypes.h>.
Fixed style bugs in the moved code. Fixed everything that depended on
the nested include. Don't include <machine/cpu.h> (in the changed files)
unless something in it is used directly.

Call identifycyrix() when 6x86MX CPU is found. The identifycyrix()
function sets cyrix_did. Old code could not display correct variable.

Reviewed by: Hideyuki Suzuki <hideyuki@sat.t.u-tokyo.ac.jp>

For AMD chips, pick up the long description from the chip if
possible. (This is not really a typographical improvement in the
case of the K6 it seems, but AMD appearantly want it too look
that way). Also if bootverbose, dump some more info about the
chip.

Treat 6x86MX CPU as 686-class CPU instead of 586-class CPU.

Removed unused #includes.

Recognize AMD K5 PR166 and PR200 CPUs.

Fill in some gaps in the cpuid features list..
bit 10 is the old bit for MTRR (presumably this changed, an older P5 I
have has got it, the newer cpus have the new MTRR bit set)
bit 11 is SEP (fast syscalls), bit 23 is MMX
Fill in the other reserved ones with a stub so that we can see them if
they turn up.

Obtained from: Intel AP-485 rev.06

Move interrupt handling code from isa.c to a new file. This should make
isa.c (slightly) more portable and will make my life developing the really
portable version much easier.

Reviewed by: peter, fsmp

- Use `6x86MX' instead of `M2'. Cyrix officially use `6x86MX' for the
CPU code-named `M2'.

- Use the result of cpuid instruction instead of DIR to identify
6x86MX cpu. DIR0 and DIR1 are not documented in the data sheet, and
cpuid instruction is enabled at reset time.

- Add a function, init_6x86MX() to initialize 6x86MX cpu. It supports
CPU_SUSP_HLT and CPU_IORT options. It always sets NC1 (640K - 1M is
not cached.), and enables L1 cache in write-back mode.

- Fix typo in the comment in identblue().

typo (Cyirx -> Cyrix).

Recognize AMD 486 CPUs.

Use `MediaGX' instead of `Gx86'.

Use `M2' instead of `6x86 with MMX'. Cyrix seems to use `M2' officially.

Man the liferafts! Here comes the long awaited SMP -> -current merge!

There are various options documented in i386/conf/LINT, there is more to
come over the next few days.

The kernel should run pretty much "as before" without the options to
activate SMP mode.

There are a handful of known "loose ends" that need to be fixed, but
have been put off since the SMP kernel is in a moderately good condition
at the moment.

This commit is the result of the tinkering and testing over the last 14
months by many people. A special thanks to Steve Passe for implementing
the APIC code!

Add new cpu type, CPU_CY486DX, which shows Cyrix 486S/DX series CPUs,
and initialization routine for those CPUs.

Tested by: Bob Bishop <rb@gid.co.uk>

Make the necessary changes so that an ELF kernel can be built. I
have successfully built, booted, and run a number of different ELF
kernel configurations, including GENERIC. LINT also builds and
links cleanly, though I have not tried to boot it.

The impact on developers is virtually nil, except for two things.
All linker sets that might possibly be present in the kernel must be
listed in "sys/i386/i386/setdefs.h". And all C symbols that are
also referenced from assembly language code must be listed in
"sys/i386/include/asnames.h". It so happens that failure to do
these things will have no impact on the a.out kernel. But it will
break the build of the ELF kernel.

The ELF bootloader works, but it is not ready to commit quite yet.

Improved CPU identification and initialization routines. This
supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD)
Nx586 CPU, and initialize special registers of Cyrix CPU and msr of
IBM Blue Lightning CPU.

If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in
write-through mode. This can be disabled by kernel configuration
options.

Reviewed by: Bruce Evans <bde@freebsd.org> and
Jordan K. Hubbard <jkh@freebsd.org>

Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not
ready for it yet.

KNF style police.

Reported by: Bruce
Thanks to: Bruce for also providing a diff.

Add bits to identify AMD K5 and K6 cpu's.
Tested only on my AMD K5 PR-133. Bit values for K6 taken from AMD document
on how to test such things.

2.2 Candidate.

Make the long-awaited change from $Id$ to $FreeBSD$

This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.

Boy, I'm glad we're not using sup anymore. This update would have been
insane otherwise.

Removed #include of "opt_temporary.h". All the temporary options went
away, so this header is no longer generated.

This change should be in 2.2. The old version shouldn;t have been in
2.2 (blush).

Replaced I586_OPTIMIZED_BCOPY and I586_OPTIMIZED_BZERO with boot-time
negative-logic flags (flags 0x01 and 0x02 for npx0, defaulting to unset = on).
This changes the default from off to on. The options have been in current
for several months with no problems reported.

Added a boot-time negative-logic flag for the old I5886_FAST_BCOPY option
which went away too soon (flag 0x04 for npx0, defaulting to unset = on).

Added a boot-time way to set the memory size (iosiz in config, iosize in
userconfig for npx0).

LINT:
Removed old options. Documented npx0's flags and iosiz.

options.i386:
Removed old options.

identcpu.c:
Don't set the function pointers here. Setting them has to be delayed
until after userconfig has had a chance to disable them and until after
a good npx0 has been detected.

machdep.c:
Use npx0's iosize instead of MAXMEM if it is nonzero.

support.s:
Added vectors and glue code for copyin() and copyout().
Fixed ifdefs for i586_bzero().
Added ifdefs for i586_bcopy().

npx.c:
Set the function pointers here.
Clear hw_float when an npx exists but is too broken to use.
Restored style from a year or three ago in npxattach().

Put I*86_CPU defines in opt_cpu.h.

Enable the i586-optimized bcopy if the cpu is a "586" and option
I586_OPTIMIZED_BCOPY is configured.

Similarly for bzero/I586_OPTIMIZED_BZERO.

Fake 586's had better have a hardware FPU with non-broken exception
handling (we mask exceptions, but broken exception handling may trap
on the instructions that do the masking). I guess this means that
the routines won't work on most 386's or FPUless 486's even when they
have a h/w FPU.

Remove devconf, it never grew up to be of any use.

Add recognition for the AMD 5x86 CPU models.

Submitted by: A JOSEPH KOSHY <koshy@india.hp.com>

Trivial cosmetic tweak to make the i[56]86 CPU MHz reprting round to the
nearest .01 Mhz rather than simply truncating it downwards.

This hack makes this 89.999928 Mhz clock correctly round to the closer
90.00-MHz rather than 89.99-MHz:
> i586 clock: 89999928 Hz, i8254 clock: 1193152 Hz
> CPU: Pentium (90.00-MHz 586-class CPU)

Eliminated i586_ctr_rate. Use i586_ctr_freq instead.

Fix something that's been bugging me for a long time: move the CPU
type identification code out of machdep.c and into a new file of its
own. Hopefully other grot can be moved out of machdep.c as well
(by other people) into more descriptively-named files.