- Copy stable/10 (r259064) to releng/10.0 as part of the
10.0-RELEASE cycle.
- Update __FreeBSD_version [1]
- Set branch name to -RC1

[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so
start releng/10.0 at '100' so the branch is started with
a value ending in zero.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Add the frame information to cpu_switch to allow us to unwind out of it,
for example when dumping threads in the kernel debugger.

Rename device vfp to option VFP and retire the ARM_VFP_SUPPORT option. This
simplifies enabling as previously both options were required to be enabled,
now we only need a single option.

While here enable VFP on the PandaBoard.

Remove the ARMFPE option. It is unsupported, and appears to be broken as
arm_fpe_core_changecontext is not a function.

Insert STOP_UNWINDING directives in the _start (kernel entry point) and
fork_trampoline (thread entry point) assembler routines, because it's
not possible to unwind beyond those points.

Also insert STOP_UNWINDING in the exception_exit routine, to prevent an
unwind-loop at that point. This is just a stopgap until we get around
to instrumenting all assembler functions with proper unwind metadata.

Add an END macro to ARM. This is mostly used to tell gas where the bounds
of the functions are when creating the EABI unwind tables.

Fix stack alignment in the kernel to be on an 8 byte boundary as required
by AAPCS.

Only spin on the blocked_lock for SCHED_ULE+SMP, as it's done on the other
arches.

Merging projects/armv6, part 1

Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms

Final whitespace trim.

Oops. ARM_RAS_END is ARM_TP_ADDRESS + 8, not 4.

Spotted out by: Mark Tinguely <tinguely at casselton d0t net>

To prevent various race conditions in the RAS code, store and restore the
values in ARM_RAS_START and ARM_RAS_END at context switch time.

MFC after: 1 week

Eliminate flushing of L2 cache in ARM context switch routines.

With VIPT L2 cache such syncing not only is redundant, but also a performance
penalty.

Pointed out by: cognet

Provide L2 cache synchronization (write back + invalidation) on ARM.

Note the cpu_l2cache_wbinv_* routines are no-ops on systems not populated with
L2 caches.

Obtained from: Marvell, Semihalf

Store the PC while context switching, for the benefits of DDB.

Improve ARM_TP_ADDRESS and RAS area.

De-hardcode usage of ARM_TP_ADDRESS and RAS local storage, and move this
special purpose page to a more convenient place i.e. after the vectors high
page, more towards the end of address space. Previous location (0xe000_0000)
caused grief if KVA was to go beyond the default limit.

Note that ARM world rebuilding is required after this change since the
location of ARM_TP_ADDRESS is shared between kernel and userland.

Submitted by: Grzegorz Bernacki (gjb AT semihalf dot com)
Reviewed by: imp
Approved by: cognet (mentor)

Do not use __XSCALE__ to detect if pld/strd/ldrd is available, use
_ARM_ARCH_5E instead.

MFC After: 3 days

Use the third argument of cpu_switch(), as done for i386/amd63, as it is
required for ULE.

Approved by: re (blanket)

Not only disable/enable interrupts, do it for FIQs as well, when needed.

Remove a never reached RET.

strd needs the destination to be double-word aligned, but the pointer passed
to savectx isn't always, so always use stmia, savectx isn't called enough
to need that kind of optimization.

Implement savectx().

Obtained from: NetBSD

Write back affected pages in pmap_qremove() as well. This removes the need
to change the DACR when switching to a kernel thread, thus making
userland thread => kernel thread => same userland thread switch cheaper by
totally avoiding data cache and TLB invalidation.

Use [ldr|str]t instead of [ldr|str] when accessing ARM_TP_ADDRESS.

In cpu_throw(), correctly calculate td->td_md.md_tp.
In cpu_switch(), set the DACR even if we're switching to a kernel thread.

Instead of using sysarch() to store-retrieve the tp, add a magic address,
ARM_TP_ADDRESS, where the tp will be stored. On CPUs that support it, a cache
line will be allocated and locked for this address, so that it will never go
to RAM. On CPUs that does not, a page is allocated for it (it will be a bit
slower, and is wrong for SMP, but should be fine for UP).
The tp is still stored in the mdthread struct, and at each context switch,
ARM_TP_ADDRESS gets updated.

Suggested by: davidxu

Start all license statements with /*-

Update the sp after popping the regs.
This is a good candidate for the golden pointy hat awards.

Save a few more cycles in cpu_switch() and cpu_throw().

Do not change the page directory and do not flush the TLB when switching to
a kernel thread.

Set the frame pointer to 0 in fork_trampoline().

Use the RET macro.

Remove useless code.

Save a few cycles in context switch.
Update comments to reflect reality.

Remove dead code.

Implement cpu_throw().

Obtained from: NetBSD

Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.