#
259065 |
|
07-Dec-2013 |
gjb |
- Copy stable/10 (r259064) to releng/10.0 as part of the 10.0-RELEASE cycle. - Update __FreeBSD_version [1] - Set branch name to -RC1
[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so start releng/10.0 at '100' so the branch is started with a value ending in zero.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
#
256281 |
|
10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
|
#
243737 |
|
30-Nov-2012 |
jkim |
Remove duplicate code. Reduce diff between amd64 and i386.
|
#
243712 |
|
30-Nov-2012 |
jkim |
Use volatile keywords properly.
|
#
243685 |
|
29-Nov-2012 |
jkim |
Tidy up inline assembly. No functional change.
|
#
241540 |
|
14-Oct-2012 |
avg |
pciereg_cfg*: use assembly to access the mem-mapped cfg space
AMD BKDG for CPU families 10h and later requires that the memory mapped config is always read into or written from al/ax/eax register.
Discussed with: kib, alc Reviewed by: kib (earlier version) MFC after: 25 days
|
#
197450 |
|
24-Sep-2009 |
avg |
number of cleanups in i386 and amd64 pci md code
o introduce PCIE_REGMAX and use it instead of ad-hoc constant o where 'reg' parameter/variable is not already unsigned, cast it to unsigned before comparison with maximum value to cut off negative values o use PCI_SLOTMAX in several places where 31 or 32 were explicitly used o drop redundant check of 'bytes' in i386 pciereg_cfgread() - valid values are already checked in the subsequent switch
Reviewed by: jhb MFC after: 1 week
|
#
192342 |
|
18-May-2009 |
jhb |
Add a read-only sysctl hw.pci.mcfg to mirror the tunable by the same name.
MFC after: 1 week
|
#
190386 |
|
24-Mar-2009 |
jhb |
Fall back to using configuration type 1 accesses for PCI config requests if the requested PCI bus falls outside of the bus range given in the ACPI MCFG table. Several BIOSes seem to not include all of the PCI busses in systems in their MCFG tables. It maybe that the BIOS is simply buggy and does support all the busses, but it is more conservative to just fall back to the old method unless it is certain that memory accesses will work.
|
#
182947 |
|
11-Sep-2008 |
jhb |
Add a 'hw.pci.mcfg' tunable. It can be set to 0 to disable memory-mapped PCI config access.
|
#
182910 |
|
10-Sep-2008 |
jhb |
Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIe memory-mapped config access. Add a workaround for these systems by checking the first function of each slot on bus 0 using both the memory-mapped config access and the older type 1 I/O port config access. If we find a slot that is only visible via the type 1 I/O port config access, we flag that slot. Future PCI config transactions to flagged slots on bus 0 use type 1 I/O port config access rather than memory mapped config access.
|
#
181987 |
|
22-Aug-2008 |
jhb |
Extend the support for PCI-e memory mapped configuration space access: - Rename pciereg_cfgopen() to pcie_cfgregopen() and expose it to the rest of the kernel. It now also accepts parameters via function arguments rather than global variables. - Add a notion of minimum and maximum bus numbers and reject requests for an out of range bus. - Add more range checks on slot/func/reg/bytes parameters to the cfg reg read/write routines. Don't panic on any invalid parameters, just fail the request (writes do nothing, reads return -1). This matches the behavior of the other cfg mechanisms. - Port the memory mapped configuration space access to amd64. On amd64 we simply use the direct map (via pmap_mapdev()) for the memory mapped window. - During acpi_attach() just after loading the ACPI tables, check for a MCFG table. If it exists, call pciereg_cfgopen() on each subtable (memory mapped window). For now we only support windows for domain 0 that start with bus 0. This removes the need for more chipset-specific quirks in the MD code. - Remove the chipset-specific quirks for the Intel 5000P/V/Z chipsets since these machines should all have MCFG tables via ACPI. - Updated pci_cfgregopen() to DTRT if ACPI had invoked pcie_cfgregopen() earlier.
MFC after: 2 weeks
|
#
174050 |
|
28-Nov-2007 |
jhb |
Adjust the code to probe for the PCI config mechanism to use. - On amd64, just assume type #1 is always used. PCI 2.0 mandated deprecated type #2 and required type #1 for all future bridges which was well before amd64 existed. - For i386, ignore whatever value was in 0xcf8 before testing for type #1 and instead rely on the other tests to determine if type #1 works. Some newer machines leave garbage in 0xcf8 during boot and as a result the kernel doesn't find PCI at all (which greatly confuses ACPI which expects PCI to exist when PCI busses are in the namespace).
MFC after: 3 days Discussed with: scottl
|
#
151643 |
|
25-Oct-2005 |
wpaul |
Modify the pci_cfgdisable() routine to bring it more in line with other OSes (Solaris, Linux, VxWorks). It's not necessary to write a 0 to the config address register when using config mechanism 1 to turn off config access. In fact, it can be downright troublesome, since it seems to confuse the PCI-PCI bridge in the AMD8111 chipset and cause it to sporadically botch reads from some devices. This is the cause of the missing USP ports problem I was experiencing with my Sun Opteron system.
Also correct the case for mechanism 2: it's only necessary to write a 0 to the ENABLE port.
|
#
140553 |
|
21-Jan-2005 |
peter |
MFi386: whitespace, copyright header, etc updates
|
#
139731 |
|
05-Jan-2005 |
imp |
Begin all license/copyright comments with /*-
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#
126926 |
|
13-Mar-2004 |
peter |
MFi386: nuke pci_cfgintr
|
#
125163 |
|
28-Jan-2004 |
peter |
MFi386: change an outb to a DELAY()
|
#
123180 |
|
06-Dec-2003 |
peter |
Various whitespace and cosmetic sync-up's with i386.
Approved by: re (scottl)
|
#
118031 |
|
25-Jul-2003 |
obrien |
Use __FBSDID().
Brought to you by: a boring talk at Ottawa Linux Symposium
|
#
114349 |
|
30-Apr-2003 |
peter |
Commit MD parts of a loosely functional AMD64 port. This is based on a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt.
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#
111068 |
|
18-Feb-2003 |
peter |
Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has been #if'ed out for a while. Complete the deed and tidy up some other bits.
We need to be able to call this stuff from outer edges of interrupt handlers for devices that have the ISR bits in pci config space. Making the bios code mpsafe was just too hairy. We had also stubbed it out some time ago due to there simply being too much brokenness in too many systems. This adds a leaf lock so that it is safe to use pci_read_config() and pci_write_config() from interrupt handlers. We still will use pcibios to do interrupt routing if there is no acpi.. [yes, I tested this]
Briefly glanced at by: imp
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#
106901 |
|
14-Nov-2002 |
imp |
MFp4: o Fix small style nit. This was supposed to be part of the last batch of style fixes, but somehow didn't get merged.
|
#
106358 |
|
02-Nov-2002 |
imp |
MFp4: o It turns out that we always need to try to route the interrupts for the case where the $PIR tells us there can be only one. Some machines require this, while others fail when we try to do this (bogusly, imho). Since we have no apriori way of knowing which is which, we always try to do the routing and hope for the best if things fail. o Add some additional comments that state the obvious, but amplify it in non-obvious ways (judging from the questions I've gotten).
This should un-break older laptops that still have to use PCIBIOS to route interrupts.
Tested by: sam
|
#
106357 |
|
02-Nov-2002 |
imp |
Use 0xffffffff instead of -1 for id to compare against. Use exact width types, since this is a MD file and won't be used elsewhere. Fix a couple of resulting printf breakages
Bug found by: phk using Flexlint
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#
104598 |
|
07-Oct-2002 |
imp |
o go ahead and route the interupt, even if it is supposedly unique. there are some strange machines that seem to need this. o delete bogus comment. o don't use the the bios for read/writing config space. They interact badly with SMP and being called from ISR. This brings -current in line with -stable.
# make the latter #ifdef on USE_PCI_BIOS_FOR_READ_WRITE in case we # need to go back in a hurry.
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#
104097 |
|
28-Sep-2002 |
phk |
Don't call function in return() for a void function.
|
#
103868 |
|
23-Sep-2002 |
jhb |
Put verbose printf's in the PCI BIOS interrupt routing code under if (bootverbose).
|
#
103711 |
|
20-Sep-2002 |
jhb |
Axe unused include.
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#
103145 |
|
09-Sep-2002 |
jhb |
Make sure a $PIR table header has a valid length before accepting the table as valid.
Submitted by: Michal Mertl <mime@traveller.cz>
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#
103043 |
|
06-Sep-2002 |
jhb |
Add a function pci_probe_route_table() that returns true if our PCI BIOS supports interrupt routing and if the specified PCI bus is present in the routing table.
|
#
103037 |
|
06-Sep-2002 |
jhb |
Dump the $PIR table if booting verbose.
|
#
103025 |
|
06-Sep-2002 |
jhb |
- Add a pci_cfgintr_valid() function to see if a given IRQ is a valid IRQ for an entry in a PCIBIOS interrupt routing ($PIR) table. - Change pci_cfgintr() to except the current IRQ of a device as a fourth argument and to use that IRQ for the device if it is valid. - If an intpin entry in a $PIR entry has a link of 0, it means that that intpin isn't connected to anything that can trigger an interrupt. Thus, test the link against 0 to find invalid entries in the table instead of implicitly relying on the irqs field to be zero. In the machines I have looked at, intpin entries with a link of 0 often have the bits for all possible interrupts for PCI devices set.
|
#
103017 |
|
06-Sep-2002 |
jhb |
Add support for printing out the contents of a PCI BIOS $PIR interrupt routing table on the console. Eventually it will be printed during verbose boots.
|
#
102976 |
|
05-Sep-2002 |
jhb |
Test PCIbios.ventry against 0 to see if we found a PCIbios entry point, not the 'entry' member. The entry point is formed from both a base and a relative entry point. 'entry' is that relative offset. It is perfectly valid to have an entry point with a relative offset of 0. PCIbios.ventry is the virtual address of the entry point that takes both 'base' and 'entry' into account, thus it is the proper variable to test to see if we have an entry point or not.
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#
100435 |
|
21-Jul-2002 |
imp |
style(9)ize the whole file
Approved in concept a long time ago by: msmith
|
#
97694 |
|
01-Jun-2002 |
imp |
Use a common function to map the bogus intlines. Don't require pin be non-zero before we map bogus intlines, always do it. This fixes a number of problems on HP Omnibook computers.
Tested/Reviewed by: Brooks Davis
|
#
97473 |
|
29-May-2002 |
brooks |
Restore the irq=0 => irq=255 hack to pci_cfgintr_search(). Just having it in pci_cfgregread() wasn't sufficent on at least the HP Omnibook 500.
Reviewed by: imp
|
#
95375 |
|
24-Apr-2002 |
imp |
o Work around bugs in the powerof2 macro: It thinks that 0 is a power of 2, but that's not the case. This fixes the case where there were slots in the PIR table that had no bits set, but we assumed they did and used strange results as a result. o Map invalid INTLINE registers to 255 in pci_cfgreg.c. This should allow us to remove the bogus checks in MI code for non-255 values.
I put these changes out for review a while ago, but no one responded to them, so into current they go.
This should help us work better on machines that don't route interrupts in the traditional way.
MFC After: 4286 millifortnights
|
#
92458 |
|
16-Mar-2002 |
imp |
Don't call the bios if the interrupt appaers to be already routed. Some older PCI BIOSes hate this and this leads to panics when it is done. Also, assume that a uniquely routed interrupt is already routed. This also seems to help some older laptops with feable BIOSes cope.
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#
89577 |
|
20-Jan-2002 |
imp |
The Libretto L series has no $PIR table, but does have a _PIR table. This typo keeps us from properly routing an interrupt for CardBus bridges on this machine. So, now we look for $PIR and then _PIR to cope. With these changes, the Libretto L1 now works properly. Evidentally, the idea comes from patch that the Japanese version of RedHat (or against a Japanese version of Red Hat), but my Japanese isn't good enough to to know for sure.
Reported by: Hiroyuki Aizu-san <eyes@navi.org>
# This may be an MFC candidate, but I'm not yet sure.
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#
86921 |
|
26-Nov-2001 |
imp |
MFS: I was confused. This code wasn't in -current after all.
Merge in the irq 0 detection. Add comment about why.
If we have irq 0, ignore it like we do irq 255. Some BIOS writers aren't careful like they should be.
|
#
82465 |
|
28-Aug-2001 |
imp |
It turns out that while Toshiba laptops don't want to route interrupts multiple times, others do. The last strategy, which was to assume that already routed interrupts were good and just return them doesn't work for some laptops. So, instead, we have a new strategy: we notice that we have an interrupt that's already routed. We go ahead and try to route it, none the less. We will assume that it is correctly routed, even if the route fails. We still assume that other failures in the bios32 call are because the interrupt is NOT routed.
Note: some laptops do not support the bios32 interface to PCI BIOS and we need to call it via the INT 2A interface. That is another windmill to till at later.
Also correct a minor typo and minor whitespace nits.
Strong MFC candidate.
|
#
82441 |
|
27-Aug-2001 |
imp |
MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure. Check return value from bios32.
[[ Yes, I was bad and committed this to stable first. I should have done the commit in the other order. ]]
|
#
82035 |
|
21-Aug-2001 |
imp |
The general conesnsus on irc was that pci bios for config registers and such was just a bad idea and one that users should be forced to enable if they want it. This patch introduces a hw.pci.enable_pcibios tunable for those people. This does not impact the pcibios interrupt routing at all.
Approved by: peter, msmith
|
#
82026 |
|
21-Aug-2001 |
peter |
Detect a certain type of PCIBIOS brain damage. For some reason, some bios vendors took it apon themselves to "censor" the host->pci bridges from PCIBIOS callers, even when the caller explicitly asks for them. This includes certain Compaq machines (eg: DL360) and some laptops.
If we detect this, shut down pcibios and revert to using IO port bashing.
Under -current, apcica does a better job anyway.
|
#
76456 |
|
11-May-2001 |
msmith |
Un-swap irq/link byte values so that printf works.
|
#
72182 |
|
08-Feb-2001 |
msmith |
Free the memory we get from devclass_get_devices and device_get_children.
Submitted by: wpaul
|
#
71237 |
|
19-Jan-2001 |
peter |
Fix a warning due to missing prototype.
|
#
70953 |
|
12-Jan-2001 |
bmilekic |
Remove declaration of airq variable from outer block. There were two declarations of a variable of the same name. The one in the outer block was unused and probably just slipped in at one point or another. This silences a compiler warning.
|
#
69783 |
|
08-Dec-2000 |
msmith |
Next phase in the PCI subsystem cleanup.
- Move PCI core code to dev/pci. - Split bridge code out into separate modules. - Remove the descriptive strings from the bridge drivers. If you want to know what a device is, use pciconf. Add support for broadly identifying devices based on class/subclass, and for parsing a preloaded device identification database so that if you want to waste the memory, you can identify *anything* we know about. - Remove machine-dependant code from the core PCI code. APIC interrupt mapping is performed by shadowing the intline register in machine- dependant code. - Bring interrupt routing support to the Alpha (although many platforms don't yet support routing or mapping interrupts entirely correctly). This resulted in spamming <sys/bus.h> into more places than it really should have gone. - Put sys/dev on the kernel/modules include path. This avoids having to change *all* the pci*.h includes.
|
#
68218 |
|
01-Nov-2000 |
msmith |
Improve the PCI interrupt routing code. Now the process is as follows:
- Look for a hardwired interrupt in the routing table for this bus/device/pin (we already did this). - Look for another device with the same link byte which has a hardwired interrupt. - Look for a PCI device matching an entry with the same link byte which has already been assigned an interrupt, and use that. - Look for a routable interrupt listed in the "PCI only" interrupts field and use that. - Pick the first interrupt that's marked as routable and use that.
|
#
67311 |
|
19-Oct-2000 |
msmith |
Call the BIOS to route the selected interrupt. Correctly calculate the interrupt from the PCI routing table (ffs returns 1 for the rightmost bit, not 0).
|
#
67186 |
|
16-Oct-2000 |
imp |
Remove debug writes introduced in prior commit
|
#
67185 |
|
16-Oct-2000 |
imp |
Add the ability to use the $PIR table in the BIOS to route interrupts on demand.
Submitted by: msmith
|
#
66529 |
|
02-Oct-2000 |
msmith |
Move the i386 PCI attachment code out of i386/isa back into i386/pci.
Split out the configuration space access primitives, as these are needed elsewhere as well.
|
#
66416 |
|
27-Sep-2000 |
peter |
Get out the roto-rooter and clean up the abuse of nexus ivars by the i386/isa/pcibus.c. This gets -current running again on multiple host->pci machines after the most recent nexus commits. I had discussed this with Mike Smith, but ended up doing it slightly differently to what we discussed as it turned out cleaner this way. Mike was suggesting creating a new resource (SYS_RES_PCIBUS) or something and using *_[gs]et_resource(), but IMHO that wasn't ideal as SYS_RES_* is meant to be a global platform property, not a quirk of a given implementation. This does use the ivar methods but does so properly. It also now prints the physical pci bus that a host->pci bridge (pcib) corresponds to.
|
#
65459 |
|
04-Sep-2000 |
peter |
Catch a few more bogosities in certain chipsets before they mess us up. Some have dual host->PCI bridges for the same logical pci bus (!), eg: some of the RCC chipsets. This is a 32/64 bit 33/66MHz and dual pci voltage motherboard so persumably there are electical or signalling differences but they are otherwise the same logical bus. The new PCI probe code however was getting somewhat upset about it and ended up creating two pci bridges to the same logical bus, which caused devices on that logical bus to appear and be probed twice.
The ACPI data on this box correctly identifies this stuff, so bring on ACPI! :-)
|
#
65304 |
|
31-Aug-2000 |
peter |
Take a shot at fixing multiple pci busses on i386. pcib_set_bus() cannot be used on the new child because it is meant to be used on the *pci* device (it looks at the parent internally) not the pcib being added. Bite the bullet and use ivars for the bus number to avoid any doubts about whether the softc is consistant between probe and attach. This should not break the Alpha code.
|
#
65176 |
|
28-Aug-2000 |
dfr |
* Completely rewrite the alpha busspace to hide the implementation from the drivers. * Remove legacy inx/outx support from chipset and replace with macros which call busspace. * Rework pci config accesses to route through the pcib device instead of calling a MD function directly.
With these changes it is possible to cleanly support machines which have more than one independantly numbered PCI busses. As a bonus, the new busspace implementation should be measurably faster than the old one.
|
#
61994 |
|
23-Jun-2000 |
msmith |
Add PnP probe methods to some common AT hardware drivers. In each case, the PnP probe is merely a stub as we make assumptions about some of this hardware before we have probed it.
Since these devices (with the exception of the speaker) are 'standard', suppress output in the !bootverbose case to clean up the probe messages somewhat.
|
#
60862 |
|
24-May-2000 |
kuriyama |
Add OPTi 82C700 chipset.
Submitted by: sanpei@sanpei.org PR: kern/18155 (part of)
|
#
60847 |
|
24-May-2000 |
kuriyama |
Add 440MX chipset.
Submitted by: YOSHIMURA Hideaki <hideakiy@cs-tokyo01.chuosystem.co.jp> References: [bsd-nomads:13764]
|
#
59978 |
|
04-May-2000 |
msmith |
Don't assume that the PCI BIOS is going to clear the unused bits in %ecx when it returns.
|
#
59294 |
|
16-Apr-2000 |
msmith |
Some more i386-only BIOS-friendliness:
- Add support for using the PCI BIOS functions for configuration space accesses, and make this the default.
- Make PNPBIOS the default (obsoletes the PNPBIOS config option).
- Add two new boot-time tunables to disable each of the above.
|
#
57402 |
|
23-Feb-2000 |
dfr |
Add a workaround to allow us to detect the second pci bus on an HP Netserver LS/2.
Approved by: jkh
|
#
57181 |
|
13-Feb-2000 |
dfr |
Fix an uninitialised variable which affected probing on some machines.
Approved by: jkh Reviewed by: gallatin
|
#
57092 |
|
09-Feb-2000 |
gallatin |
Allow allows peer pci buses which are directly connected to the RCC host pci chipset to be probed & attached on newer Dell PowerEdge servers, such as the 2400 and 4400.
Reviewed by: dfr, msmith, jlemon Tested by: hnokubi@yyy.or.jp (in a previous incantation) Approved by: jkh
|
#
57021 |
|
07-Feb-2000 |
n_hibma |
Add PCI Id's for i810 chipsets.
PR: 16517 Submitted by: SAKIYAMA Nobuo <sakichan@lares.dti.ne.jp> Approved by: jhk
|
#
55590 |
|
08-Jan-2000 |
peter |
Clean up the cfgmech/pci_mechanism debris. The reason for the existance of this is no longer an issue as we have a replacement driver for the one that needed it.
Reviewed by: dfr
|
#
54150 |
|
05-Dec-1999 |
dfr |
Don't use a bogus bus number for Ross host-pci bridges.
PR: kern/15278 Submitted by: Ahmed Benani <ahmed_benani@urbanet.ch>
|
#
54073 |
|
03-Dec-1999 |
mdodd |
Remove the 'ivars' arguement to device_add_child() and device_add_child_ordered(). 'ivars' may now be set using the device_set_ivars() function.
This makes it easier for us to change how arbitrary data structures are associated with a device_t. Eventually we won't be modifying device_t to add additional pointers for ivars, softc data etc.
Despite my best efforts I've probably forgotten something so let me know if this breaks anything. I've been running with this change for months and its been quite involved actually isolating all the changes from the rest of the local changes in my tree.
Reviewed by: peter, dfr
|
#
53363 |
|
18-Nov-1999 |
peter |
If we have found pci devices via pci_cfgopen(), but don't find a host->pci bridge specifically, then add a pcib0 device on the motherboard for the pci bus to hang off.
Requested by: Anders Andersson <anders@sanyusan.se> Obtained from: dfr
|
#
52480 |
|
25-Oct-1999 |
alc |
Add text for the AMD-751 host-to-PCI and PCI-to-PCI (AGP) bridges.
|
#
50477 |
|
27-Aug-1999 |
peter |
$Id$ -> $FreeBSD$
|
#
50182 |
|
22-Aug-1999 |
peter |
Make the identify routine add itself with priority 100 to make sure it goes after the npx/apm devices and any other motherboard devices that may get added down the track.
|
#
49601 |
|
10-Aug-1999 |
peter |
Hopefully fix the previous commit, it caused *all* bridges to be detected as PCI->HOST bridges on my (440BX) box.
My change is to remove the test at the beginning entirely, letting the switch on the device ID happen first. If the device ID is unknown, then (in the default case) check for the generic PCIS_BRIDGE_HOST tag. This should allow wierd cases (eg: wpaul's IMS VL bridge) to work by using the id override. This strategy is more in line with the other PCI match methods we use elsewhere,
I only have a limited testbed, but having my USB etc devices detected as PCI->HOST bridges doesn't look good.
|
#
49580 |
|
09-Aug-1999 |
wpaul |
Fix nexus_pcib_is_host_bridge() so that it detects my 486's PCI bus correctly. It has the following code:
if (class != PCIC_BRIDGE || subclass != PCIS_BRIDGE_HOST) return NULL;
My 486 has an Integrated Micro Solutions PCI bridge which identifies itself as subclass PCIS_BRIDGE_OTHER, not PCIS_BRIDGE_HOST. Consequently, it gets ignored. In my opinion, the correct test should be:
if ((class != PCIC_BRIDGE) && (subclass != PCIS_BRIDGE_HOST)) return NULL;
That way the test still succeeds because the chip's class is PCIC_BRIDGE. Clearly it's not reasonable to expect all host to PCI bridges to always have a subclass of PCIS_BRIDGE_HOST since I've got one that doesn't. This way the sanity test should remain relatively sane while still allowing some oddball yet correct hardware to work. If somebody has a better way to do it, go ahead and tweak the test, but be aware that class == PCIC_BRIDGE and subclass == PCIS_BRIDGE_OTHER is a valid case.
While I was here, I also added an explicit ID string for the IMS chipset. I also dealt with a minor style nit: it's bad karma not to have a default case for your switch statements, but the one in this routine doesn't have one. The default string of "Host to PCI bridge" is now assigned in a default case of the switch statement instead of initializing "s" with the string before the switch and then not having any default case.
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#
49404 |
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04-Aug-1999 |
peter |
Don't probe if pci_cfgopen() fails to find pci hardware, like we used to to. This might have caused interesting things on non-PCI hardware if PCI was compiled in.
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#
48832 |
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15-Jul-1999 |
msmith |
Add support for multiple PCI busses directly connected to the nexus. This is only partially complete, but allows 450NX-based systems with more than one PCI bus to be used again.
Submitted by: dfr
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#
47307 |
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18-May-1999 |
peter |
Move pcibus (host -> pci bus) probe/attach routines from nexus to pcibus.c. pci_cfgopen() becomes static and there are no more bus #ifdef's in nexus.c.
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#
31893 |
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20-Dec-1997 |
se |
Make the class code checks in function pci_cfgcheck less strict. It failed to recognize the PCI bus in a system that had only an old chip-set (class code 000000) and a Cyclom multiport serial card on PCI bus 0, but no VGA card or disk or network controller.
PR: i386/5300 Submitted by: Nickolay N. Dudorov <nnd@itfs.nsk.su>
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#
27555 |
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20-Jul-1997 |
bde |
Removed unused #includes.
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#
26174 |
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26-May-1997 |
se |
Yet another fix for configuration mechanism 1 register accesses: Adjust the data port address by adding the two low order bits of the register number. The address port takes only a word address (i.e. ignores the two low order bits written to it).
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#
26173 |
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26-May-1997 |
se |
Fix previous fix: The enable bit is bit 31 (0x8000000) and not bit 15.
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#
26172 |
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26-May-1997 |
se |
Set enable bit when writing the configuration address in configuration mode 1. Omission of this bit makes all config register accesses fail in on recent chip sets ...
(The problem was reported and debug output provided by: Steve Passe)
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#
26159 |
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26-May-1997 |
se |
Completely replace the PCI bus driver code to make it better reflect reality. There will be a new call interface, but for now the file pci_compat.c (which is to be deleted, after all drivers are converted) provides an emulation of the old PCI bus driver functions. The only change that might be visible to drivers is, that the type pcici_t (which had been meant to be just a handle, whose exact definition should not be relied on), has been converted into a pcicfgregs* .
The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t and has been converted to just call the PCI drivers functions to access configuration space register, instead of inventing its own ...
This code is by no means complete, but assumed to be fully operational, and brings the official code base more in line with my development code.
A new generic device descriptor data type has to be agreed on. The PCI code will then use that data type to provide new functionality:
1) userconfig support 2) "wired" PCI devices 3) conflicts checking against ISA/EISA 4) maps will depend on the command register enable bits 5) PCI to Anything bridges can be defined as devices, and are probed like any "standard" PCI device.
The following features are currently missing, but will be added back, soon:
1) unknown device probe message 2) suppression of "mirrored" devices caused by ancient, broken chip-sets
This code relies on generic shared interrupt support just commited to kern_intr.c (plus the modifications of isa.c and isa_device.h).
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24743 |
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09-Apr-1997 |
se |
Mask out revision register in consistency test of class register.
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#
24740 |
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09-Apr-1997 |
se |
Fix spelling of align and interrupt in comments.
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#
24739 |
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09-Apr-1997 |
se |
Fix consistency test to not fail on pre PCI 2.0 motherboards
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#
23415 |
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05-Mar-1997 |
se |
improve pcibus_check: Only assume PCI if at least one PCI to anything bridge on bus 0. This fixes problems with EISA-only systems mistakenly being assumed to support PCI.
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#
22975 |
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22-Feb-1997 |
peter |
Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not ready for it yet.
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#
22005 |
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25-Jan-1997 |
bde |
Sync with <pci/pcibus.h>. pcibus.c unfortunately still compiled (with only 3 or 4 warnings) when pb_maxirq went away.
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#
21673 |
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14-Jan-1997 |
jkh |
Make the long-awaited change from $Id$ to $FreeBSD$
This will make a number of things easier in the future, as well as (finally!) avoiding the Id-smashing problem which has plagued developers for so long.
Boy, I'm glad we're not using sup anymore. This update would have been insane otherwise.
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21438 |
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08-Jan-1997 |
nate |
Make the code more consistant by using the INTR*MASK macros througout the code.
Reviewed by: bde
[ Bruce suggest removing the macros completely, but I'm not up to that task quite yet. ]
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19269 |
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30-Oct-1996 |
asami |
More merge and update.
(1) deleted #if 0
pc98/pc98/mse.c
(2) hold per-unit I/O ports in ed_softc
pc98/pc98/if_ed.c pc98/pc98/if_ed98.h
(3) merge more files by segregating changes into headers.
new file (moved from pc98/pc98):
i386/isa/aic_98.h
deleted:
well, it's already in the commit message so I won't repeat the long list here ;)
Submitted by: The FreeBSD(98) Development Team
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16471 |
|
17-Jun-1996 |
bde |
Removed unused #includes of <i386/isa/icu.h> and <i386/isa/icu.h>. icu.h is only used by the icu support modules and by a few drivers that know too much about the icu (most only use it to convert `n' to `IRQn'). isa.h is only used by ioconf.c and by a few drivers that know too much about isa addresses (a few have to, because config is deficient).
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16354 |
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13-Jun-1996 |
se |
Change CONF1_ENABLE_MSK to 0x7ff00000 in another attempt to decide whether a system could possibly support PCI configuration mechanism 1 (or whether it rather is an EISA only system ...).
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#
15478 |
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30-Apr-1996 |
se |
Make pcibus_check() ignore Device/Vendor IDs of all 0.
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#
15116 |
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07-Apr-1996 |
bde |
Removed now-unused #includes of <machine/cpu.h>. They were for bootverbose being declared in the wrong place.
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14919 |
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29-Mar-1996 |
bde |
Count PCI irqs in up to 4 ISAish counters named `pci irqnn' instead of in the clk0 counter.
Reviewed by: s
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12879 |
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15-Dec-1995 |
bde |
Completed function declarations and/or added prototypes and/or added #includes to get prototypes.
pci now uses a different interrupt handler type for interrupts that it dispatches and the isa interrupt handler type for the interrupts that it handles.
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12724 |
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10-Dec-1995 |
phk |
Staticize and cleanup.
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11552 |
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17-Oct-1995 |
se |
Make CONF1_ENABLE_MSK1 even less restriktive: Ignore slot ID ...
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11544 |
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17-Oct-1995 |
se |
At least the ASUS Triton motherboards don't disable the PCI bus configuration accesses after the BIOS bus scan. The previous revision made the assumption, that every PCI motherboard did ...
Change the test on the initial value of the CONF1_ADDR_PORT register in a way that makes the probe succeed on triton based motherboards, without breaking the EISA motherboard that has some non-PCI register at the same address.
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11524 |
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15-Oct-1995 |
se |
Go back to separate tests for configuration mechanism 1 and mechanism 2. Require the state of the configuration enable bits to be OFF assuming that the BIOS left them that way, as it should anyway to avoid bad things to happen.
The tests themselves are copied from the previous release, with the exception of CONF1_ENABLE_MSK1 having the LSB set. This bit should be read back as '0', since only DWORD addresses are legal.
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11378 |
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09-Oct-1995 |
se |
Fix bad typo: CONF1_ENABLE_RES1 was written CONF1_ENABLE_CHK1 ...
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10960 |
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22-Sep-1995 |
se |
New approach to the PCI bus configuration mechanism probe problem: - try to make sure there is any kind of PCI device - if there is anything at port 0x0cf8, then check for mech. 1 or 2
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10887 |
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18-Sep-1995 |
se |
Revert most changes of previous commit. Changes relative to 1.12: - Put extra instruction between outl()/inl() sequence to prevent the old value being read back because of the bus capacitance. - Additional check for existence of register at CONF2_ENABLE_PORT.
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10807 |
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15-Sep-1995 |
se |
Another try to determine the PCI bus configuration mode (and whether there is a PCI bus at all) ...
- Do not expect the chip sets to follow even very clearly expressed requirements of the PCI 2.0 spec. - Do not read back the value just written to an I/O port without making sure that some other data have crossed the bus in between ...
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10735 |
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14-Sep-1995 |
se |
Improved verification of configuration space accesses working: Scan for devices instead of assuming that device 0 is present on bus 0 of every PCI motherboard.
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10710 |
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13-Sep-1995 |
se |
Make the PCI host bridge probe code more robust when dealing with chip sets that use configuration mode 1, but still violate the PCI 2.0 specs ... (Required for the Compaq Proliant, for example.)
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9379 |
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30-Jun-1995 |
se |
The PCI config mechanism 1 test failed for the Intel Aries. Make it less strict ...
Submitted by: NIIMI Satoshi <sa2c@and.or.jp>
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9360 |
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28-Jun-1995 |
se |
PCI configuration mechanism now determined by a method, that doesn't fail on new hardware (Compaq Prolinea and Compaq Prosignea), and that doesn't erroneously identify old mech. 2 chip sets as using mech. 1. (See section 3.6.4.1.1 of the PCI bus specs rev. 2.0)
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7254 |
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22-Mar-1995 |
se |
Correct pcibus_setup() to return as soon as one test succeeds.
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7251 |
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22-Mar-1995 |
se |
Delete PCI PCI bridge simulator code ...
Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
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7244 |
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22-Mar-1995 |
se |
Remove spurious declaration of printf().
Submitted by: Michael Reifenberger <root@rz-wb.fh-sw.de>
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7234 |
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21-Mar-1995 |
se |
New ISA specific PCI code. Supports shared PCI interrupts.
Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
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6734 |
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26-Feb-1995 |
bde |
Replace all remaining instances of `i386/include' by `machine' and fix nearby #include inconsistencies.
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6706 |
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25-Feb-1995 |
se |
Keep PCI_CONF_MODE in a safe place for later reference, if #defined.
Reviewed by: se Submitted by: seb@erix.ericsson.se (Sebastian Strollo)
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6281 |
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09-Feb-1995 |
se |
Initialisation of interrupt masks changed.
Reviewed by: se Submitted by: wolf (Wolfgang Stanglmeier)
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6104 |
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01-Feb-1995 |
se |
Reviewed by: se Submitted by: wolf (Wolfgang Stanglmeier) New ISA dependend file for PCI bus support. Replaces sys/i386/pci/pcibios.c.
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