#
343505 |
|
27-Jan-2019 |
marius |
MFC: r342634 (partial)
o Don't allocate resources for SDMA in sdhci(4) if the controller or the front-end doesn't support SDMA or the latter implements a platform- specific transfer method instead. While at it, factor out allocation and freeing of SDMA resources to sdhci_dma_{alloc,free}() in order to keep the code more readable when adding support for ADMA variants.
o Base the size of the SDMA bounce buffer on MAXPHYS up to the maximum of 512 KiB instead of using a fixed 4-KiB-buffer. With the default MAXPHYS of 128 KiB and depending on the controller and medium, this reduces the number of SDHCI interrupts by a factor of ~16 to ~32 on sequential reads while an increase of throughput of up to ~84 % was seen.
Front-ends for broken controllers that only support an SDMA buffer boundary of a specific size may set SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY and supply a size via struct sdhci_slot. According to Linux, only - unsupported in stable/10 anyway - Qualcomm MSM-type SDHCI controllers are affected by this, though.
Requested by: Shreyank Amartya (unconditional bump to 512 KiB)
o Introduce a SDHCI_DEPEND macro for specifying the dependency of the front-end modules on the sdhci(4) one and bump the module version of sdhci(4) to 2 via an also newly introduced SDHCI_VERSION in order to ensure that all components are in sync WRT struct sdhci_slot.
o In sdhci(4): - Make pointers const were applicable, and - replace a few device_printf(9) calls with slot_printf() for consistency.
|
#
340764 |
|
22-Nov-2018 |
marius |
MFC: r339007, r340543, r340654
- Add ACPI identifier for AMD eMMC 5.0 controller [1] - Add a quirk handling for AMDI0040 controllers allowing them to do HS400. [2]
Submitted by: Rajesh Kumar [1], Shreyank Amartya (original version) [2]
|
#
338636 |
|
13-Sep-2018 |
marius |
MFC: r333613
The broken DDR52 support of Intel Bay Trail eMMC controllers rumored in the commit log of r321385 has been confirmed via the public VLI54 erratum. Thus, stop advertising DDR52 for these controllers. Note that this change should hardly make a difference in practice as eMMC chips from the same era as these SoCs most likely support HS200 at least, probably even up to HS400ES.
|
#
322122 |
|
06-Aug-2017 |
marius |
MFC: r321589
- Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE} for embedded slots. Fail in the sdhci(4) initialization for slot type shared, which is completely unsupported by this driver at the moment. [1] For Intel eMMC controllers, taking the embedded slot type into account obsoltes setting SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE so remove these quirk entries. - Hide the 1.8 V VDD capability when the slot is detected as non-embedded, as the SDHCI specification explicitly states that 1.8 V VDD is applicable to embedded slots only. [2] - Define some easy bits of the SDHCI specification v4.20. [3] - Don't leak bus_dma(9) resources in failure paths of sdhci_init_slot().
Obtained from: DragonFlyBSD 65704a46 [1], 7ba10b88 [2], 0df14648 [3]
|
#
322120 |
|
06-Aug-2017 |
marius |
MFC: r319350, r320620, r321385, r321490, r321588, r321948
o Use SDHCI_CAN_DRIVE_TYPE_{A,C,D} to check for driver type support in SDHCI_CAPABILITIES2 instead of SDHCI_CTRL2_DRIVER_TYPE_{A,C,D} which are meant for setting the driver type in SDHCI_HOST_CONTROL2.
o Correct a typo in the comment part of r320577 (MFCed to stable/10 in r320899).
o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to sdhci(4), mmc(4) and mmcsd(4).
On the system where the addition of DDR52 support increased the read throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields ~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than quadrupled compared to pre-r315598 (pre-r318495 in stable/10).
However, in fact this isn't a feature-only change; there are boards based on Intel Bay Trail where DDR52 is problematic and the suggested workaround is to use HS200 mode instead. So far exact details are unknown, however, i. e. whether that's due to a defect in these SoCs or on the boards.
Moreover, due to the above changes requiring to be aware of possible MMC siblings in the fast path of mmc(4), corresponding information now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(), now longer will trigger a panic in low memory situations and all of mmc(4) operate on the same set of child devices.
o Fix a bug in the failure reporting of mmcsd_delete() that could lead to a panic.
o Fix 2 bugs on resume, one in mmcsd(4) that could lead to a panic and another one in mmc(4) that could lead to devices no longer working.
o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]
o Fix missing variable initialization in mmc_switch_status(). [2]
o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]
o Handle the case of device_add_child(9) failing, for example due to a memory shortage, gracefully in mmc(4) and sdhci(4), including not leaking memory for the instance variables in case of mmc(4), also fixing [4].
o Correctly use the size of a pointer rather than that of a pointer to a pointer (this bug was present in head r321385 only, i. e. not in a stable branch). [5]
o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd() gracefully instead of calling panic(9).
o Again, check and handle the return values of some additional function calls in mmc(4) instead of assuming that everything went right or mark non-fatal errors by casting the return value to void.
o Correct a typo in the Linux IOCTL compatibility; it should have been MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.
o Now that we are reaching ever faster speeds (more improvement in this regard is to be expected when adding ADMA support to sdhci(4)), apply a few micro-optimizations to mmc(4), mmcsd(4) and sdhci(4).
o Correct confusing and error prone mix-ups between "br" or "bridge" in mmc(4) and mmcsd(4) where - according to the terminology outlined in comments of bridge.h and mmcbr_if.m around since their addition in r163516 - the bus is meant and used instead.
o Remove comment lines from bridge.h incorrectly suggesting that there would be a MMC bridge base class driver.
o Update comments in bridge.h regarding the star topology of SD and SDIO; since version 3.00 of the SDHCI specification, for eSD and eSDIO bus topologies are actually possible in form of so called "shared buses" (in some subcontext later on renamed to "embedded" buses).
Reported by: Coverity CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4], 1378432 [5]
|
#
318497 |
|
18-May-2017 |
marius |
MFC: r318282
- Unlike as in the PCI case, when attached to ACPI, Intel Bay Trail and Braswell eMMC and SDXC controllers share the same IDs. Like in the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ quirk (see r311794 for the corresponding change to the sdhci(4) PCI PCI front-end), though. However, due to the shared ACPI IDs, this is trickier to do. - Intel Apollo Lake eMMC and SDXC controllers are affected by the APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May Lead to Unpredictable System Behavior") silicon bug. When this erratum hits, typically both SDHCI and XHCI controllers wedge. According to Intel, using ADMA2 with 64-bit addressing and 96-bit descriptors serves as a workaround. Until such times when sdhci(4) has ADMA2 support, flag DMA as broken for affected interfaces. This turns out to work around the problem, too, at the cost of performance. - In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC and SDXC controllers, too.
|
#
318495 |
|
18-May-2017 |
marius |
MFC: r315598
o Add support for eMMC DDR bus speed mode up to 52 MHz to sdhci(4) and mmc(4). Given that support for DDR52 is not denoted by SDHCI capability registers, availability of that timing is indicated by a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI controllers so far.
Compared to 50 MHz at SDR high speed typically yielding ~45 MB/s read throughput with the eMMC chips tested, read performance goes up to ~80 MB/s at DDR52.
As a side-effect, this change also fixes communication with some eMMC devices at SDR high speed mode due to the signaling voltage and UHS bits in the SDHCI controller no longer being left in an inappropriate state.
o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as hw.sdhci.quirk_set, which (when hooked up in the front-end) allow to set/clear sdhci(4) quirks for debugging and testing purposes. However, especially for SDHCI controllers on the PCI bus which have no specific support code so far and, thus, are picked up as generic SDHCI controllers, hw.sdhci.quirk_set allows for setting the necessary quirks (if required).
o In mmc(4), check and handle the return values of some more function calls instead of assuming that everything went right. In case failures actually are not problematic, indicate that by casting the return value to void.
|
#
318198 |
|
11-May-2017 |
marius |
MFC: r292180 (partial), r297127 (partial), r311911, r311923, r312939, r313250, r313712, r314811 (partial), r314887 (partial), r315430, r317981, r315466
o Move the DRIVER_MODULE() statements that declare mmc(4) to be a child of the various bridge drivers out of dev/mmc.c and into the bridge drivers.
o Add ACPI platform support for SDHCI driver.
o Fix some overly long lines, whitespace and other bugs according to style(9) as well as spelling etc. in mmc(4), mmcsd(4) and sdhci(4).
o In the mmc(4) bridges and sdhci(4) (bus) front-ends: - Remove redundant assignments of the default bus_generic_print_child device method, - use DEVMETHOD_END, - use NULL instead of 0 for pointers.
o Trim/adjust includes.
o Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges as kernel drivers and their dependency onto mmc(4).
o Add support for eMMC "partitions". Besides the user data area, i. e. the default partition, eMMC v4.41 and later devices can additionally provide up to: 1 enhanced user data area partition 2 boot partitions 1 RPMB (Replay Protected Memory Block) partition 4 general purpose partitions (optionally with a enhanced or extended attribute)
Besides simply subdividing eMMC devices, some Intel NUCs having UEFI code in the boot partitions etc., another use case for the partition support is the activation of pseudo-SLC mode, which manufacturers of eMMC chips typically associate with the enhanced user data area and/ or the enhanced attribute of general purpose partitions.
CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.
o Now that properly issuing CMD6 is crucial (so data isn't written to the wrong partition for example), make a step into the direction of correctly handling the timeout for these commands in the MMC layer. Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as recommended by relevant specifications.
o Add an IOCTL interface to mmcsd(4); this is sufficiently compatible with Linux so that the GNU mmc-utils can be ported to and used with FreeBSD (note that due to the remaining deficiencies outlined above SANITIZE operations issued by/with `mmc` currently most likely will fail). These latter have been added to ports as sysutils/mmc-utils. Among others, the `mmc` tool of mmc-utils allows for partitioning eMMC devices (tested working).
o For devices following the eMMC specification v4.41 or later, year 0 is 2013 rather than 1997; so correct this for assembling the device ID string properly.
o Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at least for some of the above a matching pair is required.
|