MFC: r319350, r320620, r321385, r321490, r321588, r321948

o Use SDHCI_CAN_DRIVE_TYPE_{A,C,D} to check for driver type support in
SDHCI_CAPABILITIES2 instead of SDHCI_CTRL2_DRIVER_TYPE_{A,C,D} which
are meant for setting the driver type in SDHCI_HOST_CONTROL2.

o Correct a typo in the comment part of r320577 (MFCed to stable/10 in
r320899).

o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to
sdhci(4), mmc(4) and mmcsd(4).

On the system where the addition of DDR52 support increased the read
throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields
~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than
quadrupled compared to pre-r315598 (pre-r318495 in stable/10).

However, in fact this isn't a feature-only change; there are boards
based on Intel Bay Trail where DDR52 is problematic and the suggested
workaround is to use HS200 mode instead. So far exact details are
unknown, however, i. e. whether that's due to a defect in these SoCs
or on the boards.

Moreover, due to the above changes requiring to be aware of possible
MMC siblings in the fast path of mmc(4), corresponding information
now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(),
now longer will trigger a panic in low memory situations and all of
mmc(4) operate on the same set of child devices.

o Fix a bug in the failure reporting of mmcsd_delete() that could lead
to a panic.

o Fix 2 bugs on resume, one in mmcsd(4) that could lead to a panic and
another one in mmc(4) that could lead to devices no longer working.

o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]

o Fix missing variable initialization in mmc_switch_status(). [2]

o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]

o Handle the case of device_add_child(9) failing, for example due to
a memory shortage, gracefully in mmc(4) and sdhci(4), including not
leaking memory for the instance variables in case of mmc(4), also
fixing [4].

o Correctly use the size of a pointer rather than that of a pointer to
a pointer (this bug was present in head r321385 only, i. e. not in a
stable branch). [5]

o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd()
gracefully instead of calling panic(9).

o Again, check and handle the return values of some additional function
calls in mmc(4) instead of assuming that everything went right or mark
non-fatal errors by casting the return value to void.

o Correct a typo in the Linux IOCTL compatibility; it should have been
MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.

o Now that we are reaching ever faster speeds (more improvement in this
regard is to be expected when adding ADMA support to sdhci(4)), apply
a few micro-optimizations to mmc(4), mmcsd(4) and sdhci(4).

o Correct confusing and error prone mix-ups between "br" or "bridge" in
mmc(4) and mmcsd(4) where - according to the terminology outlined in
comments of bridge.h and mmcbr_if.m around since their addition in
r163516 - the bus is meant and used instead.

o Remove comment lines from bridge.h incorrectly suggesting that there
would be a MMC bridge base class driver.

o Update comments in bridge.h regarding the star topology of SD and SDIO;
since version 3.00 of the SDHCI specification, for eSD and eSDIO bus
topologies are actually possible in form of so called "shared buses"
(in some subcontext later on renamed to "embedded" buses).

Reported by: Coverity
CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4],
1378432 [5]

MFC: r315598

o Add support for eMMC DDR bus speed mode up to 52 MHz to sdhci(4)
and mmc(4). Given that support for DDR52 is not denoted by SDHCI
capability registers, availability of that timing is indicated by
a new quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far.

Compared to 50 MHz at SDR high speed typically yielding ~45 MB/s
read throughput with the eMMC chips tested, read performance goes
up to ~80 MB/s at DDR52.

As a side-effect, this change also fixes communication with some
eMMC devices at SDR high speed mode due to the signaling voltage
and UHS bits in the SDHCI controller no longer being left in an
inappropriate state.

o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).

o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.

MFC: r292180 (partial), r297127 (partial), r311911, r311923, r312939,
r313250, r313712, r314811 (partial), r314887 (partial), r315430,
r317981, r315466

o Move the DRIVER_MODULE() statements that declare mmc(4) to be a child
of the various bridge drivers out of dev/mmc.c and into the bridge
drivers.

o Add ACPI platform support for SDHCI driver.

o Fix some overly long lines, whitespace and other bugs according to
style(9) as well as spelling etc. in mmc(4), mmcsd(4) and sdhci(4).

o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
- Remove redundant assignments of the default bus_generic_print_child
device method,
- use DEVMETHOD_END,
- use NULL instead of 0 for pointers.

o Trim/adjust includes.

o Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
as kernel drivers and their dependency onto mmc(4).

o Add support for eMMC "partitions". Besides the user data area, i. e.
the default partition, eMMC v4.41 and later devices can additionally
provide up to:
1 enhanced user data area partition
2 boot partitions
1 RPMB (Replay Protected Memory Block) partition
4 general purpose partitions (optionally with a enhanced or extended
attribute)

Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
code in the boot partitions etc., another use case for the partition
support is the activation of pseudo-SLC mode, which manufacturers of
eMMC chips typically associate with the enhanced user data area and/
or the enhanced attribute of general purpose partitions.

CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.

o Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications.

o Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
with Linux so that the GNU mmc-utils can be ported to and used with
FreeBSD (note that due to the remaining deficiencies outlined above
SANITIZE operations issued by/with `mmc` currently most likely will
fail). These latter have been added to ports as sysutils/mmc-utils.
Among others, the `mmc` tool of mmc-utils allows for partitioning
eMMC devices (tested working).

o For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.

o Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
least for some of the above a matching pair is required.

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

A careful reading of the disclaimer that is required to download the
SD Simplified specification, as well as other SD and SDIO
implemenations I've examined, suggest this disclaimer may be required.
It is unclear to me exactly what the license would be for, or why it
might be required. Err on the side of caution and include this
disclaimer so anybody deploying this code can judge for themselves. I
have no further unformation about the details.

Preliminary MMC stack. This stack supports SD 1.0 cards only, but
should be easily adapted to SD 2.0 (aka SDHC), SDIO, MMC and MMCplus
cards. At the present time, there's only one bridge driver for the
ARM9 based Atmel AT91RM9200.