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sdiff udiff text old ( 234761 ) new ( 234938 )
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pci_emul.c (234761) pci_emul.c (234938)
1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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59 } else { \
60 pci_set_cfgdata32((pi),(off),(val)); \
61 } \
62} while (0)
63
64#define MAXSLOTS 32
65
66static struct slotinfo {
1/*-
2 * Copyright (c) 2011 NetApp, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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59 } else { \
60 pci_set_cfgdata32((pi),(off),(val)); \
61 } \
62} while (0)
63
64#define MAXSLOTS 32
65
66static struct slotinfo {
67 char *si_name;
68 char *si_param;
67 char *si_name;
68 char *si_param;
69 struct pci_devinst *si_devi;
69 struct pci_devinst *si_devi;
70 int si_titled;
71 int si_pslot;
72 char si_prefix;
73 char si_suffix;
70 int si_titled;
71 int si_pslot;
72 char si_prefix;
73 char si_suffix;
74 int si_legacy;
74} pci_slotinfo[MAXSLOTS];
75
76/*
75} pci_slotinfo[MAXSLOTS];
76
77/*
78 * Used to keep track of legacy interrupt owners/requestors
79 */
80#define NLIRQ 16
81
82static struct lirqinfo {
83 int li_generic;
84 int li_acount;
85 struct pci_devinst *li_owner; /* XXX should be a list */
86} lirq[NLIRQ];
87
88/*
77 * NetApp specific:
78 * struct used to build an in-core OEM table to supply device names
79 * to driver instances
80 */
81static struct mptable_pci_devnames {
82#define MPT_HDR_BASE 0
83#define MPT_HDR_NAME 2
84 uint16_t md_hdrtype;

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142static void
143pci_parse_slot_usage(char *aopt)
144{
145 printf("Invalid PCI slot info field \"%s\"\n", aopt);
146 free(aopt);
147}
148
149void
89 * NetApp specific:
90 * struct used to build an in-core OEM table to supply device names
91 * to driver instances
92 */
93static struct mptable_pci_devnames {
94#define MPT_HDR_BASE 0
95#define MPT_HDR_NAME 2
96 uint16_t md_hdrtype;

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154static void
155pci_parse_slot_usage(char *aopt)
156{
157 printf("Invalid PCI slot info field \"%s\"\n", aopt);
158 free(aopt);
159}
160
161void
150pci_parse_slot(char *opt)
162pci_parse_slot(char *opt, int legacy)
151{
152 char *slot, *emul, *config;
153 char *str, *cpy;
154 int snum;
155
156 str = cpy = strdup(opt);
157 config = NULL;
158

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169
170 snum = 255;
171 snum = atoi(slot);
172 if (snum < 0 || snum >= MAXSLOTS) {
173 pci_parse_slot_usage(cpy);
174 } else {
175 pci_slotinfo[snum].si_name = emul;
176 pci_slotinfo[snum].si_param = config;
163{
164 char *slot, *emul, *config;
165 char *str, *cpy;
166 int snum;
167
168 str = cpy = strdup(opt);
169 config = NULL;
170

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181
182 snum = 255;
183 snum = atoi(slot);
184 if (snum < 0 || snum >= MAXSLOTS) {
185 pci_parse_slot_usage(cpy);
186 } else {
187 pci_slotinfo[snum].si_name = emul;
188 pci_slotinfo[snum].si_param = config;
189 pci_slotinfo[snum].si_legacy = legacy;
177 }
178}
179
180
181/*
182 *
183 * PCI MPTable names are of the form:
184 *

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372 size = 1UL << flsl(size); /* round up to a power of 2 */
373
374 switch (type) {
375 case PCIBAR_NONE:
376 baseptr = NULL;
377 addr = mask = lobits = 0;
378 break;
379 case PCIBAR_IO:
190 }
191}
192
193
194/*
195 *
196 * PCI MPTable names are of the form:
197 *

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385 size = 1UL << flsl(size); /* round up to a power of 2 */
386
387 switch (type) {
388 case PCIBAR_NONE:
389 baseptr = NULL;
390 addr = mask = lobits = 0;
391 break;
392 case PCIBAR_IO:
380 baseptr = &pci_emul_iobase;
393 if (hostbase && pci_slotinfo[pdi->pi_slot].si_legacy) {
394 assert(hostbase < PCI_EMUL_IOBASE);
395 baseptr = &hostbase;
396 } else {
397 baseptr = &pci_emul_iobase;
398 }
381 limit = PCI_EMUL_IOLIMIT;
382 mask = PCIM_BAR_IO_BASE;
383 lobits = PCIM_BAR_IO_SPACE;
384 break;
385 case PCIBAR_MEM64:
386 /*
387 * XXX
388 * Some drivers do not work well if the 64-bit BAR is allocated

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724 pde = pci_emul_finddev(si->si_name);
725 if (pde != NULL) {
726 pci_emul_init(ctx, pde, i, si->si_param);
727 pci_add_mptable_name(si);
728 }
729 }
730 }
731 pci_finish_mptable_names();
399 limit = PCI_EMUL_IOLIMIT;
400 mask = PCIM_BAR_IO_BASE;
401 lobits = PCIM_BAR_IO_SPACE;
402 break;
403 case PCIBAR_MEM64:
404 /*
405 * XXX
406 * Some drivers do not work well if the 64-bit BAR is allocated

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742 pde = pci_emul_finddev(si->si_name);
743 if (pde != NULL) {
744 pci_emul_init(ctx, pde, i, si->si_param);
745 pci_add_mptable_name(si);
746 }
747 }
748 }
749 pci_finish_mptable_names();
750
751 /*
752 * Allow ISA IRQs 5,10,11,12, and 15 to be available for
753 * generic use
754 */
755 lirq[5].li_generic = 1;
756 lirq[10].li_generic = 1;
757 lirq[11].li_generic = 1;
758 lirq[12].li_generic = 1;
759 lirq[15].li_generic = 1;
732}
733
734int
735pci_msi_enabled(struct pci_devinst *pi)
736{
737 return (pi->pi_msi.enabled);
738}
739

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752
753 if (pci_msi_enabled(pi) && msg < pci_msi_msgnum(pi)) {
754 vm_lapic_irq(pi->pi_vmctx,
755 pi->pi_msi.cpu,
756 pi->pi_msi.vector + msg);
757 }
758}
759
760}
761
762int
763pci_msi_enabled(struct pci_devinst *pi)
764{
765 return (pi->pi_msi.enabled);
766}
767

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780
781 if (pci_msi_enabled(pi) && msg < pci_msi_msgnum(pi)) {
782 vm_lapic_irq(pi->pi_vmctx,
783 pi->pi_msi.cpu,
784 pi->pi_msi.vector + msg);
785 }
786}
787
788int
789pci_is_legacy(struct pci_devinst *pi)
790{
791
792 return (pci_slotinfo[pi->pi_slot].si_legacy);
793}
794
795static int
796pci_lintr_alloc(struct pci_devinst *pi, int vec)
797{
798 int i;
799
800 assert(vec < NLIRQ);
801
802 if (vec == -1) {
803 for (i = 0; i < NLIRQ; i++) {
804 if (lirq[i].li_generic &&
805 lirq[i].li_owner == NULL) {
806 vec = i;
807 break;
808 }
809 }
810 } else {
811 if (lirq[i].li_owner != NULL) {
812 vec = -1;
813 }
814 }
815 assert(vec != -1);
816
817 lirq[vec].li_owner = pi;
818 pi->pi_lintr_pin = vec;
819
820 return (vec);
821}
822
823int
824pci_lintr_request(struct pci_devinst *pi, int vec)
825{
826
827 vec = pci_lintr_alloc(pi, vec);
828 pci_set_cfgdata8(pi, PCIR_INTLINE, vec);
829 pci_set_cfgdata8(pi, PCIR_INTPIN, 1);
830 return (0);
831}
832
833void
834pci_lintr_assert(struct pci_devinst *pi)
835{
836
837 assert(pi->pi_lintr_pin);
838 /* ioapic_assert_pin(pi->pi_vmctx, pi->pi_lintr_pin); */
839}
840
841void
842pci_lintr_deassert(struct pci_devinst *pi)
843{
844
845 assert(pi->pi_lintr_pin);
846 /* ioapic_deassert_pin(pi->pi_vmctx, pi->pi_lintr_pin); */
847}
848
849
850
760static int cfgbus, cfgslot, cfgfunc, cfgoff;
761
762static int
763pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
764 uint32_t *eax, void *arg)
765{
766 uint32_t x;
767

--- 238 unchanged lines hidden --- 		851static int cfgbus, cfgslot, cfgfunc, cfgoff;
852
853static int
854pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
855 uint32_t *eax, void *arg)
856{
857 uint32_t x;
858

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