| PPCRegisterInfo.td (263508) | PPCRegisterInfo.td (266715) |
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| 1//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 130 unchanged lines hidden (view full) --- 139def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 140def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 141def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 142def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 143def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 144def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 145} 146 | 1//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 130 unchanged lines hidden (view full) --- 139def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 140def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 141def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 142def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 143def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 144def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 145} 146 |
| 147// The full condition-code register. This is not modeled fully, but defined 148// here primarily, for compatibility with gcc, to allow the inline asm "cc" 149// clobber specification to work. 150def CC : PPCReg<"cc">, DwarfRegAlias<CR0> { 151 let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]; 152} 153 |
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| 147// Link register 148def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 149//let Aliases = [LR] in 150def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 151 152// Count register 153def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 154def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; --- 74 unchanged lines hidden (view full) --- 229def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { 230 let isAllocatable = 0; 231} 232 233def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 234def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> { 235 let CopyCost = -1; 236} | 154// Link register 155def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 156//let Aliases = [LR] in 157def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 158 159// Count register 160def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 161def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; --- 74 unchanged lines hidden (view full) --- 236def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { 237 let isAllocatable = 0; 238} 239 240def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 241def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> { 242 let CopyCost = -1; 243} |
| 244 245def CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> { 246 let isAllocatable = 0; 247} 248 |
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