1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * TI OMAP timer driver
4 *
5 * Copyright (C) 2015, Texas Instruments, Incorporated
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <timer.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/omap_common.h>
15#include <linux/bitops.h>
16
17/* Timer register bits */
18#define TCLR_START			BIT(0)	/* Start=1 */
19#define TCLR_AUTO_RELOAD		BIT(1)	/* Auto reload */
20#define TCLR_PRE_EN			BIT(5)	/* Pre-scaler enable */
21#define TCLR_PTV_SHIFT			(2)	/* Pre-scaler shift value */
22
23struct omap_gptimer_regs {
24	unsigned int tidr;		/* offset 0x00 */
25	unsigned char res1[12];
26	unsigned int tiocp_cfg;		/* offset 0x10 */
27	unsigned char res2[12];
28	unsigned int tier;		/* offset 0x20 */
29	unsigned int tistatr;		/* offset 0x24 */
30	unsigned int tistat;		/* offset 0x28 */
31	unsigned int tisr;		/* offset 0x2c */
32	unsigned int tcicr;		/* offset 0x30 */
33	unsigned int twer;		/* offset 0x34 */
34	unsigned int tclr;		/* offset 0x38 */
35	unsigned int tcrr;		/* offset 0x3c */
36	unsigned int tldr;		/* offset 0x40 */
37	unsigned int ttgr;		/* offset 0x44 */
38	unsigned int twpc;		/* offset 0x48 */
39	unsigned int tmar;		/* offset 0x4c */
40	unsigned int tcar1;		/* offset 0x50 */
41	unsigned int tscir;		/* offset 0x54 */
42	unsigned int tcar2;		/* offset 0x58 */
43};
44
45/* Omap Timer Priv */
46struct omap_timer_priv {
47	struct omap_gptimer_regs *regs;
48};
49
50static u64 omap_timer_get_count(struct udevice *dev)
51{
52	struct omap_timer_priv *priv = dev_get_priv(dev);
53
54	return timer_conv_64(readl(&priv->regs->tcrr));
55}
56
57static int omap_timer_probe(struct udevice *dev)
58{
59	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
60	struct omap_timer_priv *priv = dev_get_priv(dev);
61
62	if (!uc_priv->clock_rate)
63		uc_priv->clock_rate = V_SCLK;
64
65	uc_priv->clock_rate /= (2 << SYS_PTV);
66
67	/* start the counter ticking up, reload value on overflow */
68	writel(0, &priv->regs->tldr);
69	writel(0, &priv->regs->tcrr);
70	/* enable timer */
71	writel((SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
72	       TCLR_START, &priv->regs->tclr);
73
74	return 0;
75}
76
77static int omap_timer_of_to_plat(struct udevice *dev)
78{
79	struct omap_timer_priv *priv = dev_get_priv(dev);
80
81	priv->regs = map_physmem(dev_read_addr(dev),
82				 sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
83
84	return 0;
85}
86
87#if CONFIG_IS_ENABLED(BOOTSTAGE)
88ulong timer_get_boot_us(void)
89{
90	u64 ticks = 0;
91	u32 rate = 1;
92	u64 us;
93	int ret;
94
95	ret = dm_timer_init();
96	if (!ret) {
97		/* The timer is available */
98		rate = timer_get_rate(gd->timer);
99		timer_get_count(gd->timer, &ticks);
100	} else {
101		return 0;
102	}
103
104	us = (ticks * 1000) / rate;
105	return us;
106}
107#endif
108
109static const struct timer_ops omap_timer_ops = {
110	.get_count = omap_timer_get_count,
111};
112
113static const struct udevice_id omap_timer_ids[] = {
114	{ .compatible = "ti,am335x-timer" },
115	{ .compatible = "ti,am4372-timer" },
116	{ .compatible = "ti,omap5430-timer" },
117	{ .compatible = "ti,am654-timer" },
118	{}
119};
120
121U_BOOT_DRIVER(omap_timer) = {
122	.name	= "omap_timer",
123	.id	= UCLASS_TIMER,
124	.of_match = omap_timer_ids,
125	.of_to_plat = omap_timer_of_to_plat,
126	.priv_auto	= sizeof(struct omap_timer_priv),
127	.probe = omap_timer_probe,
128	.ops	= &omap_timer_ops,
129};
130