1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Faraday FTGMAC100 Ethernet 4 * 5 * (C) Copyright 2009 Faraday Technology 6 * Po-Yu Chuang <ratbert@faraday-tech.com> 7 * 8 * (C) Copyright 2010 Andes Technology 9 * Macpaul Lin <macpaul@andestech.com> 10 * 11 * Copyright (C) 2018, IBM Corporation. 12 */ 13 14#include <common.h> 15#include <clk.h> 16#include <reset.h> 17#include <cpu_func.h> 18#include <dm.h> 19#include <log.h> 20#include <malloc.h> 21#include <miiphy.h> 22#include <net.h> 23#include <wait_bit.h> 24#include <asm/cache.h> 25#include <dm/device_compat.h> 26#include <linux/bitops.h> 27#include <linux/io.h> 28#include <linux/iopoll.h> 29#include <linux/printk.h> 30 31#include "ftgmac100.h" 32 33/* Min frame ethernet frame size without FCS */ 34#define ETH_ZLEN 60 35 36/* Receive Buffer Size Register - HW default is 0x640 */ 37#define FTGMAC100_RBSR_DEFAULT 0x640 38 39/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ 40#define PKTBUFSTX 4 /* must be power of 2 */ 41 42/* Timeout for transmit */ 43#define FTGMAC100_TX_TIMEOUT_MS 1000 44 45/* Timeout for a mdio read/write operation */ 46#define FTGMAC100_MDIO_TIMEOUT_USEC 10000 47 48/* 49 * MDC clock cycle threshold 50 * 51 * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34 52 */ 53#define MDC_CYCTHR 0x34 54 55/* 56 * ftgmac100 model variants 57 */ 58enum ftgmac100_model { 59 FTGMAC100_MODEL_FARADAY, 60 FTGMAC100_MODEL_ASPEED, 61}; 62 63/** 64 * struct ftgmac100_data - private data for the FTGMAC100 driver 65 * 66 * @iobase: The base address of the hardware registers 67 * @txdes: The array of transmit descriptors 68 * @rxdes: The array of receive descriptors 69 * @tx_index: Transmit descriptor index in @txdes 70 * @rx_index: Receive descriptor index in @rxdes 71 * @phy_addr: The PHY interface address to use 72 * @phydev: The PHY device backing the MAC 73 * @bus: The mdio bus 74 * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...) 75 * @max_speed: Maximum speed of Ethernet connection supported by MAC 76 * @clks: The bulk of clocks assigned to the device in the DT 77 * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer 78 * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer 79 */ 80struct ftgmac100_data { 81 struct ftgmac100 *iobase; 82 83 struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN); 84 struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN); 85 int tx_index; 86 int rx_index; 87 88 u32 phy_addr; 89 struct phy_device *phydev; 90 struct mii_dev *bus; 91 u32 phy_mode; 92 u32 max_speed; 93 94 struct clk_bulk clks; 95 struct reset_ctl *reset_ctl; 96 97 /* End of RX/TX ring buffer bits. Depend on model */ 98 u32 rxdes0_edorr_mask; 99 u32 txdes0_edotr_mask; 100}; 101 102/* 103 * struct mii_bus functions 104 */ 105static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, 106 int reg_addr) 107{ 108 struct ftgmac100_data *priv = bus->priv; 109 struct ftgmac100 *ftgmac100 = priv->iobase; 110 int phycr; 111 int data; 112 int ret; 113 114 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) | 115 FTGMAC100_PHYCR_PHYAD(phy_addr) | 116 FTGMAC100_PHYCR_REGAD(reg_addr) | 117 FTGMAC100_PHYCR_MIIRD; 118 writel(phycr, &ftgmac100->phycr); 119 120 ret = readl_poll_timeout(&ftgmac100->phycr, phycr, 121 !(phycr & FTGMAC100_PHYCR_MIIRD), 122 FTGMAC100_MDIO_TIMEOUT_USEC); 123 if (ret) { 124 pr_err("%s: mdio read failed (phy:%d reg:%x)\n", 125 bus->name, phy_addr, reg_addr); 126 return ret; 127 } 128 129 data = readl(&ftgmac100->phydata); 130 131 return FTGMAC100_PHYDATA_MIIRDATA(data); 132} 133 134static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, 135 int reg_addr, u16 value) 136{ 137 struct ftgmac100_data *priv = bus->priv; 138 struct ftgmac100 *ftgmac100 = priv->iobase; 139 int phycr; 140 int data; 141 int ret; 142 143 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) | 144 FTGMAC100_PHYCR_PHYAD(phy_addr) | 145 FTGMAC100_PHYCR_REGAD(reg_addr) | 146 FTGMAC100_PHYCR_MIIWR; 147 data = FTGMAC100_PHYDATA_MIIWDATA(value); 148 149 writel(data, &ftgmac100->phydata); 150 writel(phycr, &ftgmac100->phycr); 151 152 ret = readl_poll_timeout(&ftgmac100->phycr, phycr, 153 !(phycr & FTGMAC100_PHYCR_MIIWR), 154 FTGMAC100_MDIO_TIMEOUT_USEC); 155 if (ret) { 156 pr_err("%s: mdio write failed (phy:%d reg:%x)\n", 157 bus->name, phy_addr, reg_addr); 158 } 159 160 return ret; 161} 162 163static int ftgmac100_mdio_init(struct udevice *dev) 164{ 165 struct ftgmac100_data *priv = dev_get_priv(dev); 166 struct mii_dev *bus; 167 int ret; 168 169 bus = mdio_alloc(); 170 if (!bus) 171 return -ENOMEM; 172 173 bus->read = ftgmac100_mdio_read; 174 bus->write = ftgmac100_mdio_write; 175 bus->priv = priv; 176 177 ret = mdio_register_seq(bus, dev_seq(dev)); 178 if (ret) { 179 free(bus); 180 return ret; 181 } 182 183 priv->bus = bus; 184 185 return 0; 186} 187 188static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv) 189{ 190 struct ftgmac100 *ftgmac100 = priv->iobase; 191 struct phy_device *phydev = priv->phydev; 192 u32 maccr; 193 194 if (!phydev->link && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) { 195 dev_err(phydev->dev, "No link\n"); 196 return -EREMOTEIO; 197 } 198 199 /* read MAC control register and clear related bits */ 200 maccr = readl(&ftgmac100->maccr) & 201 ~(FTGMAC100_MACCR_GIGA_MODE | 202 FTGMAC100_MACCR_FAST_MODE | 203 FTGMAC100_MACCR_FULLDUP); 204 205 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000) 206 maccr |= FTGMAC100_MACCR_GIGA_MODE; 207 208 if (phydev->speed == 100) 209 maccr |= FTGMAC100_MACCR_FAST_MODE; 210 211 if (phydev->duplex) 212 maccr |= FTGMAC100_MACCR_FULLDUP; 213 214 /* update MII config into maccr */ 215 writel(maccr, &ftgmac100->maccr); 216 217 return 0; 218} 219 220static int ftgmac100_phy_init(struct udevice *dev) 221{ 222 struct ftgmac100_data *priv = dev_get_priv(dev); 223 struct phy_device *phydev; 224 int ret; 225 226 if (IS_ENABLED(CONFIG_DM_MDIO)) 227 phydev = dm_eth_phy_connect(dev); 228 else 229 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); 230 231 if (!phydev) 232 return -ENODEV; 233 234 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI) 235 phydev->supported &= PHY_GBIT_FEATURES; 236 if (priv->max_speed) { 237 ret = phy_set_supported(phydev, priv->max_speed); 238 if (ret) 239 return ret; 240 } 241 phydev->advertising = phydev->supported; 242 priv->phydev = phydev; 243 phy_config(phydev); 244 245 return 0; 246} 247 248/* 249 * Reset MAC 250 */ 251static void ftgmac100_reset(struct ftgmac100_data *priv) 252{ 253 struct ftgmac100 *ftgmac100 = priv->iobase; 254 255 debug("%s()\n", __func__); 256 257 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST); 258 259 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) 260 ; 261} 262 263/* 264 * Set MAC address 265 */ 266static int ftgmac100_set_mac(struct ftgmac100_data *priv, 267 const unsigned char *mac) 268{ 269 struct ftgmac100 *ftgmac100 = priv->iobase; 270 unsigned int maddr = mac[0] << 8 | mac[1]; 271 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 272 273 debug("%s(%x %x)\n", __func__, maddr, laddr); 274 275 writel(maddr, &ftgmac100->mac_madr); 276 writel(laddr, &ftgmac100->mac_ladr); 277 278 return 0; 279} 280 281/* 282 * Get MAC address 283 */ 284static int ftgmac100_get_mac(struct ftgmac100_data *priv, 285 unsigned char *mac) 286{ 287 struct ftgmac100 *ftgmac100 = priv->iobase; 288 unsigned int maddr = readl(&ftgmac100->mac_madr); 289 unsigned int laddr = readl(&ftgmac100->mac_ladr); 290 291 debug("%s(%x %x)\n", __func__, maddr, laddr); 292 293 mac[0] = (maddr >> 8) & 0xff; 294 mac[1] = maddr & 0xff; 295 mac[2] = (laddr >> 24) & 0xff; 296 mac[3] = (laddr >> 16) & 0xff; 297 mac[4] = (laddr >> 8) & 0xff; 298 mac[5] = laddr & 0xff; 299 300 return 0; 301} 302 303/* 304 * disable transmitter, receiver 305 */ 306static void ftgmac100_stop(struct udevice *dev) 307{ 308 struct ftgmac100_data *priv = dev_get_priv(dev); 309 struct ftgmac100 *ftgmac100 = priv->iobase; 310 311 debug("%s()\n", __func__); 312 313 writel(0, &ftgmac100->maccr); 314 315 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI) 316 phy_shutdown(priv->phydev); 317} 318 319static int ftgmac100_start(struct udevice *dev) 320{ 321 struct eth_pdata *plat = dev_get_plat(dev); 322 struct ftgmac100_data *priv = dev_get_priv(dev); 323 struct ftgmac100 *ftgmac100 = priv->iobase; 324 struct phy_device *phydev = priv->phydev; 325 unsigned int maccr; 326 ulong start, end; 327 int ret; 328 int i; 329 330 debug("%s()\n", __func__); 331 332 ftgmac100_reset(priv); 333 334 /* set the ethernet address */ 335 ftgmac100_set_mac(priv, plat->enetaddr); 336 337 /* disable all interrupts */ 338 writel(0, &ftgmac100->ier); 339 340 /* initialize descriptors */ 341 priv->tx_index = 0; 342 priv->rx_index = 0; 343 344 for (i = 0; i < PKTBUFSTX; i++) { 345 priv->txdes[i].txdes3 = 0; 346 priv->txdes[i].txdes0 = 0; 347 } 348 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask; 349 350 start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1); 351 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN); 352 flush_dcache_range(start, end); 353 354 for (i = 0; i < PKTBUFSRX; i++) { 355 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i]; 356 priv->rxdes[i].rxdes0 = 0; 357 } 358 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask; 359 360 start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1); 361 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN); 362 flush_dcache_range(start, end); 363 364 /* transmit ring */ 365 writel((u32)priv->txdes, &ftgmac100->txr_badr); 366 367 /* receive ring */ 368 writel((u32)priv->rxdes, &ftgmac100->rxr_badr); 369 370 /* poll receive descriptor automatically */ 371 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); 372 373 /* config receive buffer size register */ 374 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr); 375 376 /* enable transmitter, receiver */ 377 maccr = FTGMAC100_MACCR_TXMAC_EN | 378 FTGMAC100_MACCR_RXMAC_EN | 379 FTGMAC100_MACCR_TXDMA_EN | 380 FTGMAC100_MACCR_RXDMA_EN | 381 FTGMAC100_MACCR_CRC_APD | 382 FTGMAC100_MACCR_FULLDUP | 383 FTGMAC100_MACCR_RX_RUNT | 384 FTGMAC100_MACCR_RX_BROADPKT; 385 386 writel(maccr, &ftgmac100->maccr); 387 388 ret = phy_startup(phydev); 389 if (ret) { 390 dev_err(phydev->dev, "Could not start PHY\n"); 391 return ret; 392 } 393 394 ret = ftgmac100_phy_adjust_link(priv); 395 if (ret) { 396 dev_err(phydev->dev, "Could not adjust link\n"); 397 return ret; 398 } 399 400 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name, 401 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr); 402 403 return 0; 404} 405 406static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length) 407{ 408 struct ftgmac100_data *priv = dev_get_priv(dev); 409 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; 410 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); 411 ulong des_end = des_start + 412 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); 413 414 /* Release buffer to DMA and flush descriptor */ 415 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; 416 flush_dcache_range(des_start, des_end); 417 418 /* Move to next descriptor */ 419 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; 420 421 return 0; 422} 423 424/* 425 * Get a data block via Ethernet 426 */ 427static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp) 428{ 429 struct ftgmac100_data *priv = dev_get_priv(dev); 430 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index]; 431 unsigned short rxlen; 432 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); 433 ulong des_end = des_start + 434 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); 435 ulong data_start = curr_des->rxdes3; 436 ulong data_end; 437 438 invalidate_dcache_range(des_start, des_end); 439 440 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) 441 return -EAGAIN; 442 443 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | 444 FTGMAC100_RXDES0_CRC_ERR | 445 FTGMAC100_RXDES0_FTL | 446 FTGMAC100_RXDES0_RUNT | 447 FTGMAC100_RXDES0_RX_ODD_NB)) { 448 return -EAGAIN; 449 } 450 451 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); 452 453 debug("%s(): RX buffer %d, %x received\n", 454 __func__, priv->rx_index, rxlen); 455 456 /* Invalidate received data */ 457 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN); 458 invalidate_dcache_range(data_start, data_end); 459 *packetp = (uchar *)data_start; 460 461 return rxlen; 462} 463 464static u32 ftgmac100_read_txdesc(const void *desc) 465{ 466 const struct ftgmac100_txdes *txdes = desc; 467 ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1); 468 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN); 469 470 invalidate_dcache_range(des_start, des_end); 471 472 return txdes->txdes0; 473} 474 475BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc) 476 477/* 478 * Send a data block via Ethernet 479 */ 480static int ftgmac100_send(struct udevice *dev, void *packet, int length) 481{ 482 struct ftgmac100_data *priv = dev_get_priv(dev); 483 struct ftgmac100 *ftgmac100 = priv->iobase; 484 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; 485 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1); 486 ulong des_end = des_start + 487 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN); 488 ulong data_start; 489 ulong data_end; 490 int rc; 491 492 invalidate_dcache_range(des_start, des_end); 493 494 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { 495 dev_err(dev, "no TX descriptor available\n"); 496 return -EPERM; 497 } 498 499 debug("%s(%x, %x)\n", __func__, (int)packet, length); 500 501 length = (length < ETH_ZLEN) ? ETH_ZLEN : length; 502 503 curr_des->txdes3 = (unsigned int)packet; 504 505 /* Flush data to be sent */ 506 data_start = curr_des->txdes3; 507 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); 508 flush_dcache_range(data_start, data_end); 509 510 /* Only one segment on TXBUF */ 511 curr_des->txdes0 &= priv->txdes0_edotr_mask; 512 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | 513 FTGMAC100_TXDES0_LTS | 514 FTGMAC100_TXDES0_TXBUF_SIZE(length) | 515 FTGMAC100_TXDES0_TXDMA_OWN ; 516 517 /* Flush modified buffer descriptor */ 518 flush_dcache_range(des_start, des_end); 519 520 /* Start transmit */ 521 writel(1, &ftgmac100->txpd); 522 523 rc = wait_for_bit_ftgmac100_txdone(curr_des, 524 FTGMAC100_TXDES0_TXDMA_OWN, false, 525 FTGMAC100_TX_TIMEOUT_MS, true); 526 if (rc) 527 return rc; 528 529 debug("%s(): packet sent\n", __func__); 530 531 /* Move to next descriptor */ 532 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; 533 534 return 0; 535} 536 537static int ftgmac100_write_hwaddr(struct udevice *dev) 538{ 539 struct eth_pdata *pdata = dev_get_plat(dev); 540 struct ftgmac100_data *priv = dev_get_priv(dev); 541 542 return ftgmac100_set_mac(priv, pdata->enetaddr); 543} 544 545static int ftgmac_read_hwaddr(struct udevice *dev) 546{ 547 struct eth_pdata *pdata = dev_get_plat(dev); 548 struct ftgmac100_data *priv = dev_get_priv(dev); 549 550 return ftgmac100_get_mac(priv, pdata->enetaddr); 551} 552 553static int ftgmac100_of_to_plat(struct udevice *dev) 554{ 555 struct eth_pdata *pdata = dev_get_plat(dev); 556 struct ftgmac100_data *priv = dev_get_priv(dev); 557 558 pdata->iobase = dev_read_addr(dev); 559 560 pdata->phy_interface = dev_read_phy_mode(dev); 561 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) 562 return -EINVAL; 563 564 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); 565 566 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) { 567 priv->rxdes0_edorr_mask = BIT(30); 568 priv->txdes0_edotr_mask = BIT(30); 569 } else { 570 priv->rxdes0_edorr_mask = BIT(15); 571 priv->txdes0_edotr_mask = BIT(15); 572 } 573 574 priv->reset_ctl = devm_reset_control_get_optional(dev, NULL); 575 576 return clk_get_bulk(dev, &priv->clks); 577} 578 579static int ftgmac100_probe(struct udevice *dev) 580{ 581 struct eth_pdata *pdata = dev_get_plat(dev); 582 struct ftgmac100_data *priv = dev_get_priv(dev); 583 int ret; 584 585 priv->iobase = (struct ftgmac100 *)pdata->iobase; 586 priv->phy_mode = pdata->phy_interface; 587 priv->max_speed = pdata->max_speed; 588 priv->phy_addr = 0; 589 590 if (dev_read_bool(dev, "use-ncsi")) 591 priv->phy_mode = PHY_INTERFACE_MODE_NCSI; 592 593#ifdef CONFIG_PHY_ADDR 594 priv->phy_addr = CONFIG_PHY_ADDR; 595#endif 596 597 ret = clk_enable_bulk(&priv->clks); 598 if (ret) 599 goto out; 600 601 if (priv->reset_ctl) { 602 ret = reset_deassert(priv->reset_ctl); 603 if (ret) 604 goto out; 605 } 606 607 /* 608 * If DM MDIO is enabled, the MDIO bus will be initialized later in 609 * dm_eth_phy_connect 610 */ 611 if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI && 612 !IS_ENABLED(CONFIG_DM_MDIO)) { 613 ret = ftgmac100_mdio_init(dev); 614 if (ret) { 615 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); 616 goto out; 617 } 618 } 619 620 ret = ftgmac100_phy_init(dev); 621 if (ret) { 622 dev_err(dev, "Failed to initialize PHY: %d\n", ret); 623 goto out; 624 } 625 626 ftgmac_read_hwaddr(dev); 627 628out: 629 if (ret) 630 clk_release_bulk(&priv->clks); 631 632 return ret; 633} 634 635static int ftgmac100_remove(struct udevice *dev) 636{ 637 struct ftgmac100_data *priv = dev_get_priv(dev); 638 639 free(priv->phydev); 640 mdio_unregister(priv->bus); 641 mdio_free(priv->bus); 642 if (priv->reset_ctl) 643 reset_assert(priv->reset_ctl); 644 clk_release_bulk(&priv->clks); 645 646 return 0; 647} 648 649static const struct eth_ops ftgmac100_ops = { 650 .start = ftgmac100_start, 651 .send = ftgmac100_send, 652 .recv = ftgmac100_recv, 653 .stop = ftgmac100_stop, 654 .free_pkt = ftgmac100_free_pkt, 655 .write_hwaddr = ftgmac100_write_hwaddr, 656}; 657 658static const struct udevice_id ftgmac100_ids[] = { 659 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY }, 660 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED }, 661 { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED }, 662 { } 663}; 664 665U_BOOT_DRIVER(ftgmac100) = { 666 .name = "ftgmac100", 667 .id = UCLASS_ETH, 668 .of_match = ftgmac100_ids, 669 .of_to_plat = ftgmac100_of_to_plat, 670 .probe = ftgmac100_probe, 671 .remove = ftgmac100_remove, 672 .ops = &ftgmac100_ops, 673 .priv_auto = sizeof(struct ftgmac100_data), 674 .plat_auto = sizeof(struct eth_pdata), 675 .flags = DM_FLAG_ALLOC_PRIV_DMA, 676}; 677