1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014 Panasonic Corporation 4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com> 5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers. 6 */ 7 8#include <common.h> 9#include <dm.h> 10#include <malloc.h> 11#include <nand.h> 12#include <asm/cache.h> 13#include <asm/dma-mapping.h> 14#include <dm/device_compat.h> 15#include <dm/devres.h> 16#include <linux/bitfield.h> 17#include <linux/bitops.h> 18#include <linux/delay.h> 19#include <linux/dma-direction.h> 20#include <linux/dma-mapping.h> 21#include <linux/err.h> 22#include <linux/errno.h> 23#include <linux/io.h> 24#include <linux/mtd/mtd.h> 25#include <linux/mtd/rawnand.h> 26 27#include "denali.h" 28 29#define DENALI_NAND_NAME "denali-nand" 30 31/* for Indexed Addressing */ 32#define DENALI_INDEXED_CTRL 0x00 33#define DENALI_INDEXED_DATA 0x10 34 35#define DENALI_MAP00 (0 << 26) /* direct access to buffer */ 36#define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */ 37#define DENALI_MAP10 (2 << 26) /* high-level control plane */ 38#define DENALI_MAP11 (3 << 26) /* direct controller access */ 39 40/* MAP11 access cycle type */ 41#define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */ 42#define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */ 43#define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */ 44 45/* MAP10 commands */ 46#define DENALI_ERASE 0x01 47 48#define DENALI_BANK(denali) ((denali)->active_bank << 24) 49 50#define DENALI_INVALID_BANK -1 51#define DENALI_NR_BANKS 4 52 53static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) 54{ 55 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); 56} 57 58/* 59 * Direct Addressing - the slave address forms the control information (command 60 * type, bank, block, and page address). The slave data is the actual data to 61 * be transferred. This mode requires 28 bits of address region allocated. 62 */ 63static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr) 64{ 65 return ioread32(denali->host + addr); 66} 67 68static void denali_direct_write(struct denali_nand_info *denali, u32 addr, 69 u32 data) 70{ 71 iowrite32(data, denali->host + addr); 72} 73 74/* 75 * Indexed Addressing - address translation module intervenes in passing the 76 * control information. This mode reduces the required address range. The 77 * control information and transferred data are latched by the registers in 78 * the translation module. 79 */ 80static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr) 81{ 82 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); 83 return ioread32(denali->host + DENALI_INDEXED_DATA); 84} 85 86static void denali_indexed_write(struct denali_nand_info *denali, u32 addr, 87 u32 data) 88{ 89 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); 90 iowrite32(data, denali->host + DENALI_INDEXED_DATA); 91} 92 93/* 94 * Use the configuration feature register to determine the maximum number of 95 * banks that the hardware supports. 96 */ 97static void denali_detect_max_banks(struct denali_nand_info *denali) 98{ 99 uint32_t features = ioread32(denali->reg + FEATURES); 100 101 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features); 102 103 /* the encoding changed from rev 5.0 to 5.1 */ 104 if (denali->revision < 0x0501) 105 denali->max_banks <<= 1; 106} 107 108static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali) 109{ 110 int i; 111 112 for (i = 0; i < DENALI_NR_BANKS; i++) 113 iowrite32(U32_MAX, denali->reg + INTR_EN(i)); 114 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); 115} 116 117static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali) 118{ 119 int i; 120 121 for (i = 0; i < DENALI_NR_BANKS; i++) 122 iowrite32(0, denali->reg + INTR_EN(i)); 123 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); 124} 125 126static void denali_clear_irq(struct denali_nand_info *denali, 127 int bank, uint32_t irq_status) 128{ 129 /* write one to clear bits */ 130 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); 131} 132 133static void denali_clear_irq_all(struct denali_nand_info *denali) 134{ 135 int i; 136 137 for (i = 0; i < DENALI_NR_BANKS; i++) 138 denali_clear_irq(denali, i, U32_MAX); 139} 140 141static void __denali_check_irq(struct denali_nand_info *denali) 142{ 143 uint32_t irq_status; 144 int i; 145 146 for (i = 0; i < DENALI_NR_BANKS; i++) { 147 irq_status = ioread32(denali->reg + INTR_STATUS(i)); 148 denali_clear_irq(denali, i, irq_status); 149 150 if (i != denali->active_bank) 151 continue; 152 153 denali->irq_status |= irq_status; 154 } 155} 156 157static void denali_reset_irq(struct denali_nand_info *denali) 158{ 159 denali->irq_status = 0; 160 denali->irq_mask = 0; 161} 162 163static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, 164 uint32_t irq_mask) 165{ 166 unsigned long time_left = 1000000; 167 168 while (time_left) { 169 __denali_check_irq(denali); 170 171 if (irq_mask & denali->irq_status) 172 return denali->irq_status; 173 udelay(1); 174 time_left--; 175 } 176 177 if (!time_left) { 178 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", 179 irq_mask); 180 return 0; 181 } 182 183 return denali->irq_status; 184} 185 186static uint32_t denali_check_irq(struct denali_nand_info *denali) 187{ 188 __denali_check_irq(denali); 189 190 return denali->irq_status; 191} 192 193static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 194{ 195 struct denali_nand_info *denali = mtd_to_denali(mtd); 196 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 197 int i; 198 199 for (i = 0; i < len; i++) 200 buf[i] = denali->host_read(denali, addr); 201} 202 203static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 204{ 205 struct denali_nand_info *denali = mtd_to_denali(mtd); 206 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 207 int i; 208 209 for (i = 0; i < len; i++) 210 denali->host_write(denali, addr, buf[i]); 211} 212 213static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) 214{ 215 struct denali_nand_info *denali = mtd_to_denali(mtd); 216 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 217 uint16_t *buf16 = (uint16_t *)buf; 218 int i; 219 220 for (i = 0; i < len / 2; i++) 221 buf16[i] = denali->host_read(denali, addr); 222} 223 224static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf, 225 int len) 226{ 227 struct denali_nand_info *denali = mtd_to_denali(mtd); 228 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 229 const uint16_t *buf16 = (const uint16_t *)buf; 230 int i; 231 232 for (i = 0; i < len / 2; i++) 233 denali->host_write(denali, addr, buf16[i]); 234} 235 236static uint8_t denali_read_byte(struct mtd_info *mtd) 237{ 238 uint8_t byte; 239 240 denali_read_buf(mtd, &byte, 1); 241 242 return byte; 243} 244 245static void denali_write_byte(struct mtd_info *mtd, uint8_t byte) 246{ 247 denali_write_buf(mtd, &byte, 1); 248} 249 250static uint16_t denali_read_word(struct mtd_info *mtd) 251{ 252 uint16_t word; 253 254 denali_read_buf16(mtd, (uint8_t *)&word, 2); 255 256 return word; 257} 258 259static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) 260{ 261 struct denali_nand_info *denali = mtd_to_denali(mtd); 262 uint32_t type; 263 264 if (ctrl & NAND_CLE) 265 type = DENALI_MAP11_CMD; 266 else if (ctrl & NAND_ALE) 267 type = DENALI_MAP11_ADDR; 268 else 269 return; 270 271 /* 272 * Some commands are followed by chip->dev_ready or chip->waitfunc. 273 * irq_status must be cleared here to catch the R/B# interrupt later. 274 */ 275 if (ctrl & NAND_CTRL_CHANGE) 276 denali_reset_irq(denali); 277 278 denali->host_write(denali, DENALI_BANK(denali) | type, dat); 279} 280 281static int denali_dev_ready(struct mtd_info *mtd) 282{ 283 struct denali_nand_info *denali = mtd_to_denali(mtd); 284 285 return !!(denali_check_irq(denali) & INTR__INT_ACT); 286} 287 288static int denali_check_erased_page(struct mtd_info *mtd, 289 struct nand_chip *chip, uint8_t *buf, 290 unsigned long uncor_ecc_flags, 291 unsigned int max_bitflips) 292{ 293 uint8_t *ecc_code = chip->buffers->ecccode; 294 int ecc_steps = chip->ecc.steps; 295 int ecc_size = chip->ecc.size; 296 int ecc_bytes = chip->ecc.bytes; 297 int i, ret, stat; 298 299 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 300 chip->ecc.total); 301 if (ret) 302 return ret; 303 304 for (i = 0; i < ecc_steps; i++) { 305 if (!(uncor_ecc_flags & BIT(i))) 306 continue; 307 308 stat = nand_check_erased_ecc_chunk(buf, ecc_size, 309 ecc_code, ecc_bytes, 310 NULL, 0, 311 chip->ecc.strength); 312 if (stat < 0) { 313 mtd->ecc_stats.failed++; 314 } else { 315 mtd->ecc_stats.corrected += stat; 316 max_bitflips = max_t(unsigned int, max_bitflips, stat); 317 } 318 319 buf += ecc_size; 320 ecc_code += ecc_bytes; 321 } 322 323 return max_bitflips; 324} 325 326static int denali_hw_ecc_fixup(struct mtd_info *mtd, 327 struct denali_nand_info *denali, 328 unsigned long *uncor_ecc_flags) 329{ 330 struct nand_chip *chip = mtd_to_nand(mtd); 331 int bank = denali->active_bank; 332 uint32_t ecc_cor; 333 unsigned int max_bitflips; 334 335 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); 336 ecc_cor >>= ECC_COR_INFO__SHIFT(bank); 337 338 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) { 339 /* 340 * This flag is set when uncorrectable error occurs at least in 341 * one ECC sector. We can not know "how many sectors", or 342 * "which sector(s)". We need erase-page check for all sectors. 343 */ 344 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0); 345 return 0; 346 } 347 348 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor); 349 350 /* 351 * The register holds the maximum of per-sector corrected bitflips. 352 * This is suitable for the return value of the ->read_page() callback. 353 * Unfortunately, we can not know the total number of corrected bits in 354 * the page. Increase the stats by max_bitflips. (compromised solution) 355 */ 356 mtd->ecc_stats.corrected += max_bitflips; 357 358 return max_bitflips; 359} 360 361static int denali_sw_ecc_fixup(struct mtd_info *mtd, 362 struct denali_nand_info *denali, 363 unsigned long *uncor_ecc_flags, uint8_t *buf) 364{ 365 unsigned int ecc_size = denali->nand.ecc.size; 366 unsigned int bitflips = 0; 367 unsigned int max_bitflips = 0; 368 uint32_t err_addr, err_cor_info; 369 unsigned int err_byte, err_sector, err_device; 370 uint8_t err_cor_value; 371 unsigned int prev_sector = 0; 372 uint32_t irq_status; 373 374 denali_reset_irq(denali); 375 376 do { 377 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); 378 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr); 379 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr); 380 381 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); 382 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE, 383 err_cor_info); 384 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE, 385 err_cor_info); 386 387 /* reset the bitflip counter when crossing ECC sector */ 388 if (err_sector != prev_sector) 389 bitflips = 0; 390 391 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) { 392 /* 393 * Check later if this is a real ECC error, or 394 * an erased sector. 395 */ 396 *uncor_ecc_flags |= BIT(err_sector); 397 } else if (err_byte < ecc_size) { 398 /* 399 * If err_byte is larger than ecc_size, means error 400 * happened in OOB, so we ignore it. It's no need for 401 * us to correct it err_device is represented the NAND 402 * error bits are happened in if there are more than 403 * one NAND connected. 404 */ 405 int offset; 406 unsigned int flips_in_byte; 407 408 offset = (err_sector * ecc_size + err_byte) * 409 denali->devs_per_cs + err_device; 410 411 /* correct the ECC error */ 412 flips_in_byte = hweight8(buf[offset] ^ err_cor_value); 413 buf[offset] ^= err_cor_value; 414 mtd->ecc_stats.corrected += flips_in_byte; 415 bitflips += flips_in_byte; 416 417 max_bitflips = max(max_bitflips, bitflips); 418 } 419 420 prev_sector = err_sector; 421 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR)); 422 423 /* 424 * Once handle all ECC errors, controller will trigger an 425 * ECC_TRANSACTION_DONE interrupt. 426 */ 427 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); 428 if (!(irq_status & INTR__ECC_TRANSACTION_DONE)) 429 return -EIO; 430 431 return max_bitflips; 432} 433 434static void denali_setup_dma64(struct denali_nand_info *denali, 435 dma_addr_t dma_addr, int page, int write) 436{ 437 uint32_t mode; 438 const int page_count = 1; 439 440 mode = DENALI_MAP10 | DENALI_BANK(denali) | page; 441 442 /* DMA is a three step process */ 443 444 /* 445 * 1. setup transfer type, interrupt when complete, 446 * burst len = 64 bytes, the number of pages 447 */ 448 denali->host_write(denali, mode, 449 0x01002000 | (64 << 16) | (write << 8) | page_count); 450 451 /* 2. set memory low address */ 452 denali->host_write(denali, mode, lower_32_bits(dma_addr)); 453 454 /* 3. set memory high address */ 455 denali->host_write(denali, mode, upper_32_bits(dma_addr)); 456} 457 458static void denali_setup_dma32(struct denali_nand_info *denali, 459 dma_addr_t dma_addr, int page, int write) 460{ 461 uint32_t mode; 462 const int page_count = 1; 463 464 mode = DENALI_MAP10 | DENALI_BANK(denali); 465 466 /* DMA is a four step process */ 467 468 /* 1. setup transfer type and # of pages */ 469 denali->host_write(denali, mode | page, 470 0x2000 | (write << 8) | page_count); 471 472 /* 2. set memory high address bits 23:8 */ 473 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); 474 475 /* 3. set memory low address bits 23:8 */ 476 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); 477 478 /* 4. interrupt when complete, burst len = 64 bytes */ 479 denali->host_write(denali, mode | 0x14000, 0x2400); 480} 481 482static int denali_pio_read(struct denali_nand_info *denali, void *buf, 483 size_t size, int page, int raw) 484{ 485 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; 486 uint32_t *buf32 = (uint32_t *)buf; 487 uint32_t irq_status, ecc_err_mask; 488 int i; 489 490 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) 491 ecc_err_mask = INTR__ECC_UNCOR_ERR; 492 else 493 ecc_err_mask = INTR__ECC_ERR; 494 495 denali_reset_irq(denali); 496 497 for (i = 0; i < size / 4; i++) 498 *buf32++ = denali->host_read(denali, addr); 499 500 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); 501 if (!(irq_status & INTR__PAGE_XFER_INC)) 502 return -EIO; 503 504 if (irq_status & INTR__ERASED_PAGE) 505 memset(buf, 0xff, size); 506 507 return irq_status & ecc_err_mask ? -EBADMSG : 0; 508} 509 510static int denali_pio_write(struct denali_nand_info *denali, 511 const void *buf, size_t size, int page, int raw) 512{ 513 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; 514 const uint32_t *buf32 = (uint32_t *)buf; 515 uint32_t irq_status; 516 int i; 517 518 denali_reset_irq(denali); 519 520 for (i = 0; i < size / 4; i++) 521 denali->host_write(denali, addr, *buf32++); 522 523 irq_status = denali_wait_for_irq(denali, 524 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL); 525 if (!(irq_status & INTR__PROGRAM_COMP)) 526 return -EIO; 527 528 return 0; 529} 530 531static int denali_pio_xfer(struct denali_nand_info *denali, void *buf, 532 size_t size, int page, int raw, int write) 533{ 534 if (write) 535 return denali_pio_write(denali, buf, size, page, raw); 536 else 537 return denali_pio_read(denali, buf, size, page, raw); 538} 539 540static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, 541 size_t size, int page, int raw, int write) 542{ 543 dma_addr_t dma_addr; 544 uint32_t irq_mask, irq_status, ecc_err_mask; 545 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 546 int ret = 0; 547 548 dma_addr = dma_map_single(buf, size, dir); 549 if (dma_mapping_error(denali->dev, dma_addr)) { 550 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n"); 551 return denali_pio_xfer(denali, buf, size, page, raw, write); 552 } 553 554 if (write) { 555 /* 556 * INTR__PROGRAM_COMP is never asserted for the DMA transfer. 557 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted 558 * when the page program is completed. 559 */ 560 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL; 561 ecc_err_mask = 0; 562 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) { 563 irq_mask = INTR__DMA_CMD_COMP; 564 ecc_err_mask = INTR__ECC_UNCOR_ERR; 565 } else { 566 irq_mask = INTR__DMA_CMD_COMP; 567 ecc_err_mask = INTR__ECC_ERR; 568 } 569 570 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); 571 /* 572 * The ->setup_dma() hook kicks DMA by using the data/command 573 * interface, which belongs to a different AXI port from the 574 * register interface. Read back the register to avoid a race. 575 */ 576 ioread32(denali->reg + DMA_ENABLE); 577 578 denali_reset_irq(denali); 579 denali->setup_dma(denali, dma_addr, page, write); 580 581 irq_status = denali_wait_for_irq(denali, irq_mask); 582 if (!(irq_status & INTR__DMA_CMD_COMP)) 583 ret = -EIO; 584 else if (irq_status & ecc_err_mask) 585 ret = -EBADMSG; 586 587 iowrite32(0, denali->reg + DMA_ENABLE); 588 589 dma_unmap_single(dma_addr, size, dir); 590 591 if (irq_status & INTR__ERASED_PAGE) 592 memset(buf, 0xff, size); 593 594 return ret; 595} 596 597static int denali_data_xfer(struct denali_nand_info *denali, void *buf, 598 size_t size, int page, int raw, int write) 599{ 600 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); 601 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0, 602 denali->reg + TRANSFER_SPARE_REG); 603 604 if (denali->dma_avail) 605 return denali_dma_xfer(denali, buf, size, page, raw, write); 606 else 607 return denali_pio_xfer(denali, buf, size, page, raw, write); 608} 609 610static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip, 611 int page, int write) 612{ 613 struct denali_nand_info *denali = mtd_to_denali(mtd); 614 unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0; 615 unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT; 616 int writesize = mtd->writesize; 617 int oobsize = mtd->oobsize; 618 uint8_t *bufpoi = chip->oob_poi; 619 int ecc_steps = chip->ecc.steps; 620 int ecc_size = chip->ecc.size; 621 int ecc_bytes = chip->ecc.bytes; 622 int oob_skip = denali->oob_skip_bytes; 623 size_t size = writesize + oobsize; 624 int i, pos, len; 625 626 /* BBM at the beginning of the OOB area */ 627 chip->cmdfunc(mtd, start_cmd, writesize, page); 628 if (write) 629 chip->write_buf(mtd, bufpoi, oob_skip); 630 else 631 chip->read_buf(mtd, bufpoi, oob_skip); 632 bufpoi += oob_skip; 633 634 /* OOB ECC */ 635 for (i = 0; i < ecc_steps; i++) { 636 pos = ecc_size + i * (ecc_size + ecc_bytes); 637 len = ecc_bytes; 638 639 if (pos >= writesize) 640 pos += oob_skip; 641 else if (pos + len > writesize) 642 len = writesize - pos; 643 644 chip->cmdfunc(mtd, rnd_cmd, pos, -1); 645 if (write) 646 chip->write_buf(mtd, bufpoi, len); 647 else 648 chip->read_buf(mtd, bufpoi, len); 649 bufpoi += len; 650 if (len < ecc_bytes) { 651 len = ecc_bytes - len; 652 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1); 653 if (write) 654 chip->write_buf(mtd, bufpoi, len); 655 else 656 chip->read_buf(mtd, bufpoi, len); 657 bufpoi += len; 658 } 659 } 660 661 /* OOB free */ 662 len = oobsize - (bufpoi - chip->oob_poi); 663 chip->cmdfunc(mtd, rnd_cmd, size - len, -1); 664 if (write) 665 chip->write_buf(mtd, bufpoi, len); 666 else 667 chip->read_buf(mtd, bufpoi, len); 668} 669 670static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 671 uint8_t *buf, int oob_required, int page) 672{ 673 struct denali_nand_info *denali = mtd_to_denali(mtd); 674 int writesize = mtd->writesize; 675 int oobsize = mtd->oobsize; 676 int ecc_steps = chip->ecc.steps; 677 int ecc_size = chip->ecc.size; 678 int ecc_bytes = chip->ecc.bytes; 679 void *tmp_buf = denali->buf; 680 int oob_skip = denali->oob_skip_bytes; 681 size_t size = writesize + oobsize; 682 int ret, i, pos, len; 683 684 ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0); 685 if (ret) 686 return ret; 687 688 /* Arrange the buffer for syndrome payload/ecc layout */ 689 if (buf) { 690 for (i = 0; i < ecc_steps; i++) { 691 pos = i * (ecc_size + ecc_bytes); 692 len = ecc_size; 693 694 if (pos >= writesize) 695 pos += oob_skip; 696 else if (pos + len > writesize) 697 len = writesize - pos; 698 699 memcpy(buf, tmp_buf + pos, len); 700 buf += len; 701 if (len < ecc_size) { 702 len = ecc_size - len; 703 memcpy(buf, tmp_buf + writesize + oob_skip, 704 len); 705 buf += len; 706 } 707 } 708 } 709 710 if (oob_required) { 711 uint8_t *oob = chip->oob_poi; 712 713 /* BBM at the beginning of the OOB area */ 714 memcpy(oob, tmp_buf + writesize, oob_skip); 715 oob += oob_skip; 716 717 /* OOB ECC */ 718 for (i = 0; i < ecc_steps; i++) { 719 pos = ecc_size + i * (ecc_size + ecc_bytes); 720 len = ecc_bytes; 721 722 if (pos >= writesize) 723 pos += oob_skip; 724 else if (pos + len > writesize) 725 len = writesize - pos; 726 727 memcpy(oob, tmp_buf + pos, len); 728 oob += len; 729 if (len < ecc_bytes) { 730 len = ecc_bytes - len; 731 memcpy(oob, tmp_buf + writesize + oob_skip, 732 len); 733 oob += len; 734 } 735 } 736 737 /* OOB free */ 738 len = oobsize - (oob - chip->oob_poi); 739 memcpy(oob, tmp_buf + size - len, len); 740 } 741 742 return 0; 743} 744 745static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 746 int page) 747{ 748 denali_oob_xfer(mtd, chip, page, 0); 749 750 return 0; 751} 752 753static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 754 int page) 755{ 756 struct denali_nand_info *denali = mtd_to_denali(mtd); 757 int status; 758 759 denali_reset_irq(denali); 760 761 denali_oob_xfer(mtd, chip, page, 1); 762 763 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 764 status = chip->waitfunc(mtd, chip); 765 766 return status & NAND_STATUS_FAIL ? -EIO : 0; 767} 768 769static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, 770 uint8_t *buf, int oob_required, int page) 771{ 772 struct denali_nand_info *denali = mtd_to_denali(mtd); 773 unsigned long uncor_ecc_flags = 0; 774 int stat = 0; 775 int ret; 776 777 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0); 778 if (ret && ret != -EBADMSG) 779 return ret; 780 781 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) 782 stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags); 783 else if (ret == -EBADMSG) 784 stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf); 785 786 if (stat < 0) 787 return stat; 788 789 if (uncor_ecc_flags) { 790 ret = denali_read_oob(mtd, chip, page); 791 if (ret) 792 return ret; 793 794 stat = denali_check_erased_page(mtd, chip, buf, 795 uncor_ecc_flags, stat); 796 } 797 798 return stat; 799} 800 801static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 802 const uint8_t *buf, int oob_required, int page) 803{ 804 struct denali_nand_info *denali = mtd_to_denali(mtd); 805 int writesize = mtd->writesize; 806 int oobsize = mtd->oobsize; 807 int ecc_steps = chip->ecc.steps; 808 int ecc_size = chip->ecc.size; 809 int ecc_bytes = chip->ecc.bytes; 810 void *tmp_buf = denali->buf; 811 int oob_skip = denali->oob_skip_bytes; 812 size_t size = writesize + oobsize; 813 int i, pos, len; 814 815 /* 816 * Fill the buffer with 0xff first except the full page transfer. 817 * This simplifies the logic. 818 */ 819 if (!buf || !oob_required) 820 memset(tmp_buf, 0xff, size); 821 822 /* Arrange the buffer for syndrome payload/ecc layout */ 823 if (buf) { 824 for (i = 0; i < ecc_steps; i++) { 825 pos = i * (ecc_size + ecc_bytes); 826 len = ecc_size; 827 828 if (pos >= writesize) 829 pos += oob_skip; 830 else if (pos + len > writesize) 831 len = writesize - pos; 832 833 memcpy(tmp_buf + pos, buf, len); 834 buf += len; 835 if (len < ecc_size) { 836 len = ecc_size - len; 837 memcpy(tmp_buf + writesize + oob_skip, buf, 838 len); 839 buf += len; 840 } 841 } 842 } 843 844 if (oob_required) { 845 const uint8_t *oob = chip->oob_poi; 846 847 /* BBM at the beginning of the OOB area */ 848 memcpy(tmp_buf + writesize, oob, oob_skip); 849 oob += oob_skip; 850 851 /* OOB ECC */ 852 for (i = 0; i < ecc_steps; i++) { 853 pos = ecc_size + i * (ecc_size + ecc_bytes); 854 len = ecc_bytes; 855 856 if (pos >= writesize) 857 pos += oob_skip; 858 else if (pos + len > writesize) 859 len = writesize - pos; 860 861 memcpy(tmp_buf + pos, oob, len); 862 oob += len; 863 if (len < ecc_bytes) { 864 len = ecc_bytes - len; 865 memcpy(tmp_buf + writesize + oob_skip, oob, 866 len); 867 oob += len; 868 } 869 } 870 871 /* OOB free */ 872 len = oobsize - (oob - chip->oob_poi); 873 memcpy(tmp_buf + size - len, oob, len); 874 } 875 876 return denali_data_xfer(denali, tmp_buf, size, page, 1, 1); 877} 878 879static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, 880 const uint8_t *buf, int oob_required, int page) 881{ 882 struct denali_nand_info *denali = mtd_to_denali(mtd); 883 884 return denali_data_xfer(denali, (void *)buf, mtd->writesize, 885 page, 0, 1); 886} 887 888static void denali_select_chip(struct mtd_info *mtd, int chip) 889{ 890 struct denali_nand_info *denali = mtd_to_denali(mtd); 891 892 denali->active_bank = chip; 893} 894 895static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) 896{ 897 struct denali_nand_info *denali = mtd_to_denali(mtd); 898 uint32_t irq_status; 899 900 /* R/B# pin transitioned from low to high? */ 901 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT); 902 903 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL; 904} 905 906static int denali_erase(struct mtd_info *mtd, int page) 907{ 908 struct denali_nand_info *denali = mtd_to_denali(mtd); 909 uint32_t irq_status; 910 911 denali_reset_irq(denali); 912 913 denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page, 914 DENALI_ERASE); 915 916 /* wait for erase to complete or failure to occur */ 917 irq_status = denali_wait_for_irq(denali, 918 INTR__ERASE_COMP | INTR__ERASE_FAIL); 919 920 return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL; 921} 922 923static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, 924 const struct nand_data_interface *conf) 925{ 926 struct denali_nand_info *denali = mtd_to_denali(mtd); 927 const struct nand_sdr_timings *timings; 928 unsigned long t_x, mult_x; 929 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; 930 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; 931 int addr_2_data_mask; 932 uint32_t tmp; 933 934 timings = nand_get_sdr_timings(conf); 935 if (IS_ERR(timings)) 936 return PTR_ERR(timings); 937 938 /* clk_x period in picoseconds */ 939 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); 940 if (!t_x) 941 return -EINVAL; 942 943 /* 944 * The bus interface clock, clk_x, is phase aligned with the core clock. 945 * The clk_x is an integral multiple N of the core clk. The value N is 946 * configured at IP delivery time, and its available value is 4, 5, 6. 947 */ 948 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); 949 if (mult_x < 4 || mult_x > 6) 950 return -EINVAL; 951 952 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 953 return 0; 954 955 /* tREA -> ACC_CLKS */ 956 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); 957 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); 958 959 tmp = ioread32(denali->reg + ACC_CLKS); 960 tmp &= ~ACC_CLKS__VALUE; 961 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks); 962 iowrite32(tmp, denali->reg + ACC_CLKS); 963 964 /* tRWH -> RE_2_WE */ 965 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); 966 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); 967 968 tmp = ioread32(denali->reg + RE_2_WE); 969 tmp &= ~RE_2_WE__VALUE; 970 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we); 971 iowrite32(tmp, denali->reg + RE_2_WE); 972 973 /* tRHZ -> RE_2_RE */ 974 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); 975 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); 976 977 tmp = ioread32(denali->reg + RE_2_RE); 978 tmp &= ~RE_2_RE__VALUE; 979 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); 980 iowrite32(tmp, denali->reg + RE_2_RE); 981 982 /* 983 * tCCS, tWHR -> WE_2_RE 984 * 985 * With WE_2_RE properly set, the Denali controller automatically takes 986 * care of the delay; the driver need not set NAND_WAIT_TCCS. 987 */ 988 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); 989 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); 990 991 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); 992 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; 993 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re); 994 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); 995 996 /* tADL -> ADDR_2_DATA */ 997 998 /* for older versions, ADDR_2_DATA is only 6 bit wide */ 999 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; 1000 if (denali->revision < 0x0501) 1001 addr_2_data_mask >>= 1; 1002 1003 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); 1004 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); 1005 1006 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); 1007 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; 1008 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data); 1009 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); 1010 1011 /* tREH, tWH -> RDWR_EN_HI_CNT */ 1012 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), 1013 t_x); 1014 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); 1015 1016 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); 1017 tmp &= ~RDWR_EN_HI_CNT__VALUE; 1018 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi); 1019 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); 1020 1021 /* tRP, tWP -> RDWR_EN_LO_CNT */ 1022 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); 1023 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), 1024 t_x); 1025 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x); 1026 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); 1027 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); 1028 1029 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); 1030 tmp &= ~RDWR_EN_LO_CNT__VALUE; 1031 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo); 1032 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); 1033 1034 /* tCS, tCEA -> CS_SETUP_CNT */ 1035 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, 1036 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, 1037 0); 1038 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); 1039 1040 tmp = ioread32(denali->reg + CS_SETUP_CNT); 1041 tmp &= ~CS_SETUP_CNT__VALUE; 1042 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup); 1043 iowrite32(tmp, denali->reg + CS_SETUP_CNT); 1044 1045 return 0; 1046} 1047 1048static void denali_reset_banks(struct denali_nand_info *denali) 1049{ 1050 u32 irq_status; 1051 int i; 1052 1053 for (i = 0; i < denali->max_banks; i++) { 1054 denali->active_bank = i; 1055 1056 denali_reset_irq(denali); 1057 1058 iowrite32(DEVICE_RESET__BANK(i), 1059 denali->reg + DEVICE_RESET); 1060 1061 irq_status = denali_wait_for_irq(denali, 1062 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT); 1063 if (!(irq_status & INTR__INT_ACT)) 1064 break; 1065 } 1066 1067 dev_dbg(denali->dev, "%d chips connected\n", i); 1068 denali->max_banks = i; 1069} 1070 1071static void denali_hw_init(struct denali_nand_info *denali) 1072{ 1073 /* 1074 * The REVISION register may not be reliable. Platforms are allowed to 1075 * override it. 1076 */ 1077 if (!denali->revision) 1078 denali->revision = swab16(ioread32(denali->reg + REVISION)); 1079 1080 /* 1081 * Set how many bytes should be skipped before writing data in OOB. 1082 * If a platform requests a non-zero value, set it to the register. 1083 * Otherwise, read the value out, expecting it has already been set up 1084 * by firmware. 1085 */ 1086 if (denali->oob_skip_bytes) 1087 iowrite32(denali->oob_skip_bytes, 1088 denali->reg + SPARE_AREA_SKIP_BYTES); 1089 else 1090 denali->oob_skip_bytes = ioread32(denali->reg + 1091 SPARE_AREA_SKIP_BYTES); 1092 1093 denali_detect_max_banks(denali); 1094 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED); 1095 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); 1096 1097 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); 1098 iowrite32(WRITE_PROTECT__FLAG, denali->reg + WRITE_PROTECT); 1099} 1100 1101int denali_calc_ecc_bytes(int step_size, int strength) 1102{ 1103 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */ 1104 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2; 1105} 1106EXPORT_SYMBOL(denali_calc_ecc_bytes); 1107 1108static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip, 1109 struct denali_nand_info *denali) 1110{ 1111 int oobavail = mtd->oobsize - denali->oob_skip_bytes; 1112 int ret; 1113 1114 /* 1115 * If .size and .strength are already set (usually by DT), 1116 * check if they are supported by this controller. 1117 */ 1118 if (chip->ecc.size && chip->ecc.strength) 1119 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail); 1120 1121 /* 1122 * We want .size and .strength closest to the chip's requirement 1123 * unless NAND_ECC_MAXIMIZE is requested. 1124 */ 1125 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) { 1126 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail); 1127 if (!ret) 1128 return 0; 1129 } 1130 1131 /* Max ECC strength is the last thing we can do */ 1132 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail); 1133} 1134 1135static struct nand_ecclayout nand_oob; 1136 1137static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, 1138 struct mtd_oob_region *oobregion) 1139{ 1140 struct denali_nand_info *denali = mtd_to_denali(mtd); 1141 struct nand_chip *chip = mtd_to_nand(mtd); 1142 1143 if (section) 1144 return -ERANGE; 1145 1146 oobregion->offset = denali->oob_skip_bytes; 1147 oobregion->length = chip->ecc.total; 1148 1149 return 0; 1150} 1151 1152static int denali_ooblayout_free(struct mtd_info *mtd, int section, 1153 struct mtd_oob_region *oobregion) 1154{ 1155 struct denali_nand_info *denali = mtd_to_denali(mtd); 1156 struct nand_chip *chip = mtd_to_nand(mtd); 1157 1158 if (section) 1159 return -ERANGE; 1160 1161 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; 1162 oobregion->length = mtd->oobsize - oobregion->offset; 1163 1164 return 0; 1165} 1166 1167static const struct mtd_ooblayout_ops denali_ooblayout_ops = { 1168 .ecc = denali_ooblayout_ecc, 1169 .rfree = denali_ooblayout_free, 1170}; 1171 1172static int denali_multidev_fixup(struct denali_nand_info *denali) 1173{ 1174 struct nand_chip *chip = &denali->nand; 1175 struct mtd_info *mtd = nand_to_mtd(chip); 1176 1177 /* 1178 * Support for multi device: 1179 * When the IP configuration is x16 capable and two x8 chips are 1180 * connected in parallel, DEVICES_CONNECTED should be set to 2. 1181 * In this case, the core framework knows nothing about this fact, 1182 * so we should tell it the _logical_ pagesize and anything necessary. 1183 */ 1184 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); 1185 1186 /* 1187 * On some SoCs, DEVICES_CONNECTED is not auto-detected. 1188 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case. 1189 */ 1190 if (denali->devs_per_cs == 0) { 1191 denali->devs_per_cs = 1; 1192 iowrite32(1, denali->reg + DEVICES_CONNECTED); 1193 } 1194 1195 if (denali->devs_per_cs == 1) 1196 return 0; 1197 1198 if (denali->devs_per_cs != 2) { 1199 dev_err(denali->dev, "unsupported number of devices %d\n", 1200 denali->devs_per_cs); 1201 return -EINVAL; 1202 } 1203 1204 /* 2 chips in parallel */ 1205 mtd->size <<= 1; 1206 mtd->erasesize <<= 1; 1207 mtd->writesize <<= 1; 1208 mtd->oobsize <<= 1; 1209 chip->chipsize <<= 1; 1210 chip->page_shift += 1; 1211 chip->phys_erase_shift += 1; 1212 chip->bbt_erase_shift += 1; 1213 chip->chip_shift += 1; 1214 chip->pagemask <<= 1; 1215 chip->ecc.size <<= 1; 1216 chip->ecc.bytes <<= 1; 1217 chip->ecc.strength <<= 1; 1218 denali->oob_skip_bytes <<= 1; 1219 1220 return 0; 1221} 1222 1223int denali_wait_reset_complete(struct denali_nand_info *denali) 1224{ 1225 u32 irq_status; 1226 1227 irq_status = denali_wait_for_irq(denali, INTR__RST_COMP); 1228 if (!(irq_status & INTR__RST_COMP)) 1229 return -EIO; 1230 1231 return 0; 1232} 1233 1234int denali_init(struct denali_nand_info *denali) 1235{ 1236 struct nand_chip *chip = &denali->nand; 1237 struct mtd_info *mtd = nand_to_mtd(chip); 1238 u32 features = ioread32(denali->reg + FEATURES); 1239 int ret; 1240 1241 denali_hw_init(denali); 1242 1243 denali_clear_irq_all(denali); 1244 1245 denali_reset_banks(denali); 1246 1247 denali->active_bank = DENALI_INVALID_BANK; 1248 1249 chip->flash_node = dev_ofnode(denali->dev); 1250 /* Fallback to the default name if DT did not give "label" property */ 1251 if (!mtd->name) 1252 mtd->name = "denali-nand"; 1253 1254 chip->select_chip = denali_select_chip; 1255 chip->read_byte = denali_read_byte; 1256 chip->write_byte = denali_write_byte; 1257 chip->read_word = denali_read_word; 1258 chip->cmd_ctrl = denali_cmd_ctrl; 1259 chip->dev_ready = denali_dev_ready; 1260 chip->waitfunc = denali_waitfunc; 1261 1262 if (features & FEATURES__INDEX_ADDR) { 1263 denali->host_read = denali_indexed_read; 1264 denali->host_write = denali_indexed_write; 1265 } else { 1266 denali->host_read = denali_direct_read; 1267 denali->host_write = denali_direct_write; 1268 } 1269 1270 /* clk rate info is needed for setup_data_interface */ 1271 if (denali->clk_x_rate) 1272 chip->setup_data_interface = denali_setup_data_interface; 1273 1274 ret = nand_scan_ident(mtd, denali->max_banks, NULL); 1275 if (ret) 1276 return ret; 1277 1278 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA) 1279 denali->dma_avail = 1; 1280 1281 if (denali->dma_avail) { 1282 chip->buf_align = ARCH_DMA_MINALIGN; 1283 if (denali->caps & DENALI_CAP_DMA_64BIT) 1284 denali->setup_dma = denali_setup_dma64; 1285 else 1286 denali->setup_dma = denali_setup_dma32; 1287 } else { 1288 chip->buf_align = 4; 1289 } 1290 1291 chip->options |= NAND_USE_BOUNCE_BUFFER; 1292 chip->bbt_options |= NAND_BBT_USE_FLASH; 1293 chip->bbt_options |= NAND_BBT_NO_OOB; 1294 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 1295 1296 /* no subpage writes on denali */ 1297 chip->options |= NAND_NO_SUBPAGE_WRITE; 1298 1299 ret = denali_ecc_setup(mtd, chip, denali); 1300 if (ret) { 1301 dev_err(denali->dev, "Failed to setup ECC settings.\n"); 1302 return ret; 1303 } 1304 1305 dev_dbg(denali->dev, 1306 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", 1307 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); 1308 1309 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | 1310 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), 1311 denali->reg + ECC_CORRECTION); 1312 iowrite32(mtd->erasesize / mtd->writesize, 1313 denali->reg + PAGES_PER_BLOCK); 1314 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, 1315 denali->reg + DEVICE_WIDTH); 1316 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG, 1317 denali->reg + TWO_ROW_ADDR_CYCLES); 1318 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); 1319 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); 1320 1321 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); 1322 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); 1323 /* chip->ecc.steps is set by nand_scan_tail(); not available here */ 1324 iowrite32(mtd->writesize / chip->ecc.size, 1325 denali->reg + CFG_NUM_DATA_BLOCKS); 1326 1327 mtd_set_ooblayout(mtd, &denali_ooblayout_ops); 1328 1329 nand_oob.eccbytes = denali->nand.ecc.bytes; 1330 denali->nand.ecc.layout = &nand_oob; 1331 1332 if (chip->options & NAND_BUSWIDTH_16) { 1333 chip->read_buf = denali_read_buf16; 1334 chip->write_buf = denali_write_buf16; 1335 } else { 1336 chip->read_buf = denali_read_buf; 1337 chip->write_buf = denali_write_buf; 1338 } 1339 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS; 1340 chip->ecc.read_page = denali_read_page; 1341 chip->ecc.read_page_raw = denali_read_page_raw; 1342 chip->ecc.write_page = denali_write_page; 1343 chip->ecc.write_page_raw = denali_write_page_raw; 1344 chip->ecc.read_oob = denali_read_oob; 1345 chip->ecc.write_oob = denali_write_oob; 1346 chip->erase = denali_erase; 1347 1348 ret = denali_multidev_fixup(denali); 1349 if (ret) 1350 return ret; 1351 1352 /* 1353 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not 1354 * use devm_kmalloc() because the memory allocated by devm_ does not 1355 * guarantee DMA-safe alignment. 1356 */ 1357 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); 1358 if (!denali->buf) 1359 return -ENOMEM; 1360 1361 ret = nand_scan_tail(mtd); 1362 if (ret) 1363 goto free_buf; 1364 1365 ret = nand_register(0, mtd); 1366 if (ret) { 1367 dev_err(denali->dev, "Failed to register MTD: %d\n", ret); 1368 goto free_buf; 1369 } 1370 return 0; 1371 1372free_buf: 1373 kfree(denali->buf); 1374 1375 return ret; 1376} 1377